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dBCool(R) Remote Thermal Controller and Voltage Monitor ADT7466
FEATURES
Monitors two analog voltages or thermistor temperature inputs One on-chip and up to two remote temperature sensors with series resistance cancellation Controls and monitors the speed of up to two fans Automatic fan speed control mode controls system cooling based on measured temperature Enhanced acoustic mode dramatically reduces user perception of changing fan speeds Thermal protection feature via THERM output monitors performance impact of Intel(R) Pentium(R) 4 processor thermal control circuit via PROCHOT input 3-wire fan speed measurement Limit comparison of all monitored values SMBus 1.1 serial interface
GENERAL DESCRIPTION
The ADT7466 dBCool controller is a complete thermal monitor and dual fan controller for noise-sensitive applications requiring active system cooling. It can monitor two analog voltages or the temperature of two thermistors, plus its own supply voltage. It can monitor the temperature of up to two remote sensor diodes, plus its own internal temperature. It can measure and control the speed of up to two fans so that they operate at the lowest possible speed for minimum acoustic noise. The automatic fan speed control loop optimizes fan speed for a given temperature. The effectiveness of the system's thermal solution can be monitored using the PROCHOT input to time and monitor the PROCHOT output of the processor.
APPLICATIONS
Low acoustic noise notebook PCs
FUNCTIONAL BLOCK DIAGRAM
VCC SCL SDA ALERT
DRIVE1
8-BIT DAC V_FAN_MIN V_FAN_ON CONTROL
ACOUSTIC ENHANCEMENT CONTROL
SERIAL BUS INTERFACE ADDRESS POINTER REGISTER CONFIGURATION REGISTERS THERM REGISTER INTERRUPT MASKING INTERRUPT STATUS REGISTERS
DRIVE2
8-BIT DAC AUTOMATIC FAN SPEED CONTROL FAN SPEED MONITOR FAN1 ENABLE
TACH1 TACH2 FANLOCK FAN1_ON/ PROCHOT/ THERM
PROCHOT D1+ D1- SERIES RESISTANCE CANCELLATION SERIES RESISTANCE CANCELLATION BAND GAP TEMPERATURE SENSOR INPUT SIGNAL CONDITIONING AND ANALOG MULTIPLEXER
10-BIT ADC
LIMIT COMPARATORS
AIN1/TH1/D2- AIN2/TH2/D2+
BAND GAP REFERENCE
VALUE AND LIMIT REGISTERS
GND
REFOUT
Figure 1.
Protected by U.S. Patent Numbers 6,188,189; 6,169,442; 6,097,239; 5,982,221; 5,867,012.
04711-001
ADT7466
(c)2010 SCILLC. All rights reserved. May 2010 - Rev. 3
Publication Order Number: ADT7466/D
ADT7466 TABLE OF CONTENTS
Specifications..................................................................................... 3 Serial Bus Timing ......................................................................... 5 Absolute Maximum Ratings............................................................ 6 Thermal Characteristics .............................................................. 6 ESD Caution .................................................................................. 6 Pin Configuration and Function Descriptions ............................. 7 Typical Performance Characteristics ............................................. 8 Functional Description .................................................................. 11 Measurement Inputs .................................................................. 11 Sequential Measurement ........................................................... 11 Fan Speed Measurement and Control ..................................... 11 Internal Registers of the ADT7466........................................... 11 Theory of Operation ...................................................................... 12 Serial Bus Interface ..................................................................... 12 Write and Read Operations....................................................... 14 Alert Response Address (ARA) ................................................ 15 SMBus Timeout .......................................................................... 15 Voltage Measurement ................................................................ 15 Reference Voltage Output.......................................................... 16 Configuration of Pin 11 and Pin 12 ......................................... 16 Temperature Measurement ....................................................... 17 Series Resistance Cancellation .................................................. 17 Temperature Measurement Method ........................................ 17 Using Discrete Transistors......................................................... 17 Temperature Measurement Using Thermistors ..................... 19 Reading Temperature from the ADT7466 .............................. 21 Additional ADC Functions ....................................................... 22 Limit Values ................................................................................ 22 Alert Interrupt Behavior............................................................ 23 Configuring the ADT7466 THERM Pin as an Output ......... 26 Fan Drive ..................................................................................... 27 PWM or Switch Mode Fan Drive ............................................. 27 Fan Speed Measurement ........................................................... 27 Fan Start-Up Timeout ................................................................ 29 Automatic Fan Speed Control .................................................. 30 Starting the Fan .......................................................................... 31 XOR Test Mode ............................................................................... 32 Application Circuit ......................................................................... 33 ADT7466 Register Map ................................................................. 34 Register Details ........................................................................... 36 Outline Dimensions ....................................................................... 48 Ordering Guide .......................................................................... 48
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ADT7466 SPECIFICATIONS
TA = TMIN to TMAX, VCC = VMIN to VMAX, unless otherwise noted.1 Table 1.
Parameter POWER SUPPLY Supply Voltage Supply Current, ICC TEMPERATURE-TO-DIGITAL CONVERTER Local Sensor Accuracy Resolution Remote Diode Sensor Accuracy 0.25 1 3 5 0.25 192 72 12 0 2 Min 3.0 Typ 3.3 1.4 30 Max 5.5 3 70 Unit V mA A Test Conditions/Comments
Interface inactive, ADC active Standby mode, digital inputs low
1 3
Resolution Remote Sensor Source Current
Series Resistance Cancellation THERMISTOR-TO-DIGITAL CONVERTER Temperature Range Resolution Accuracy ANALOG-TO-DIGITAL CONVERTER Input Voltage Range Total Unadjusted Error (TUE) Differential Nonlinearity (DNL) Power Supply Sensitivity Conversion Time (AIN Input) Conversion Time (Local Temperature) Conversion Time (Remote Temperature) Conversion Time (VCC) Total Monitoring Cycle Time Total Monitoring Cycle Time FAN RPM-TO-DIGITAL CONVERTER Accuracy Full-Scale Count Nominal Input RPM
C C C C C C C A A A k
20C TA 60C; VCC = 3.3 V -40C TA +125C; VCC = 3.3 V 20C TA 60C; -40C TD +125C; VCC = 3.3 V -40C TA +105C; -40C TD +125C; VCC = 3.3 V -40C TA +125C; -40C TD +125C High level Mid level Low level Maximum resistance in series with thermal diode that can be cancelled out Range over which specified accuracy is achieved. Wider range can be used with less accuracy. Using specified thermistor and application circuit over specified temperature range VREF = 2.25V
30 0.25 2
100
C C C
0 1 1 8.30 8.63 35.22 7.93 68.38 87
VREF 2.5 1 8.65 8.99 36.69 8.26 71.24 90.63
V % LSB %/V ms ms ms ms ms ms
Averaging enabled Averaging enabled Averaging enabled Averaging enabled Averaging enabled, Pin 11 and Pin 12 configured for AIN/TH monitoring (see Table 15) Averaging enabled, Pin 11 and Pin 12 configured for REM2 monitoring (see Table 15)
4 65,535 109 329 5000 10000 81.92
% RPM RPM RPM RPM kHz Fan count = 0xBFFF Fan count = 0x3FFF Fan count = 0x0438 Fan count = 0x021C
Internal Clock Frequency
78.64
85.12
Rev. 3 | Page 3 of 48 | www.onsemi.com
ADT7466
Parameter DRIVE OUTPUTS (DRIVE1, DRIVE2) Output Voltage Range Output Source Current Output Sink Current DAC Resolution Monotonicity Differential Nonlinearity Integral Nonlinearity Total Unadjusted Error REFERENCE VOLTAGE OUTPUT (REFOUT) Output Voltage Output Source Current Output Sink Current OPEN-DRAIN SERIAL DATA BUS OUTPUT (SDA) Output Low Voltage (VOL) High Level Output Current (IOH) DIGITAL INPUTS (SCL, SDA, TACH INPUTS, PROCHOT) Input High Voltage (VIH) Input Low Voltage (VIL) Hysteresis DIGITAL INPUT CURRENT (TACH INPUTS, PROCHOT) Input High Current (IIH) Input Low Current (IIL) Input Capacitance (IN) OPEN-DRAIN DIGITAL OUTPUTS (ALERT, FANLOCK, FAN1_ON/THERM) Output Low Voltage (VOL) High Level Output Current (IOH) SERIAL BUS TIMING 2 Clock Frequency (fSCLK) Glitch Immunity (tSW) Bus Free Time (tBUF) Start Setup Time (tSU;STA) Start Hold Time (tHD;STA) SCL Low Time (tLOW) SCL High Time (tHIGH) SCL, SDA Rise Time (tr) SCL, SDA Fall Time (tf ) Data Setup Time (tSU;DAT) Detect Clock Low Timeout (tTIMEOUT)
1
Min
Typ 0-2.2 2 0.5
Max
Unit V mA mA Bits Bits LSB LSB %
Test Conditions/Comments Digital input = 0x00 to 0xFF
8 8 1 1 5
IL = 2 mA
2.226
2.25
2.288 10 0.6
V mA mA
0.1
0.4 1
V A
IOUT = -4.0 mA, VCC = 3.3 V VOUT = VCC
2.0 0.8 0.5
V V V
-1 1 20
A A pF
VIN = VCC VIN = 0
0.1
0.4 1 400 50
V A kHz ns s s s s s ns ns ns Ms
IOUT = -4.0 mA, VCC = 3.3 V VOUT =VCC See Figure 2 See Figure 2 See Figure 2 See Figure 2 See Figure 2 See Figure 2 See Figure 2 See Figure 2 See Figure 2 See Figure 2 Can be optionally disabled
1.3 0.6 0.6 1.3 0.6 1000 300 100 25 64
All voltages are measured with respect to GND, unless otherwise specified. Typical values are at TA = 25C and represent the most likely parametric norm. Logic inputs accept input high voltages up to 5 V even when the device is operating at supply voltages below 5 V. Timing specifications are tested at logic levels of VIL = 0.8 V for a falling edge and at VIH = 2.0 V for a rising edge. 2 Guaranteed by design, not production tested.
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ADT7466
SERIAL BUS TIMING
tR
SCL
tF
t HD; ST A
t LO W t HD;S TA t HD;DAT t SU; DAT
04711-003
t HI G H
t S U; STA
t SU;S TO
SDA
t BUF
P S S P
Figure 2. Diagram for Serial Bus Timing
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ADT7466 ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter Positive Supply Voltage (VCC) Voltage on Any Other Pin Input Current at Any Pin Package Input Current Maximum Junction Temperature (TJ max) Storage Temperature Range Lead Temperature, Soldering: IR Peak Reflow Temperature Lead Temperature (10 sec) ESD Rating Rating 6.5 V -0.3 V to 6.5 V 5 mA 20 mA 150C -65C to +150C 220C 300C 2000 V
Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
THERMAL CHARACTERISTICS
16-Lead QSOP Package: JA = 105C/W JC = 39C/W
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
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ADT7466 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
DRIVE1 1 TACH1 2 DRIVE2 3 TACH2 4
16 SCL 15 SDA 13 REFOUT TOP VIEW GND 5 (Not to Scale) 12 AIN2/TH2/D2+
ADT7466
14 ALERT
VCC 6 FAN1_ON/PROCHOT/THERM 7 FANLOCK 8
11 AIN1/TH1/D2- 10 D1+
04711-002
9
D1-
Figure 3. Pin Configuration
Table 3. Pin Function Descriptions
Pin No. 1 2 3 4 5 6 7 Mnemonic DRIVE1 TACH1 DRIVE2 TACH2 GND VCC FAN1_ON/ PROCHOT/ THERM Type Analog Output Digital Input Analog Output Digital Input Ground Power supply Digital I/O Description Output of 8-Bit DAC Controlling Fan 1 Speed. Fan Tachometer Input to Measure Speed of Fan 1. Output of 8-Bit DAC Controlling Fan 2 Speed. Fan Tachometer Input to Measure Speed of Fan 2. Ground Pin for Analog and Digital Circuitry. 3.3 V Power Supply. VCC is also monitored through this pin. If configured as FAN1_ON, this pin is the open-drain control signal output for the dc-dc converter. Active (high) when DRIVE1 > V_FAN_MIN. If configured as PROCHOT, the input can be connected to the PROCHOT output of the Intel Pentium 4 processor to time and monitor PROCHOT assertions. If configured as THERM, this pin is the interrupt output to flag critical thermal events. 8 9 10 11 12 13 14 15 16 FANLOCK D1- D1+ AIN1/TH1/D2- AIN2(TH2)/D2+ REFOUT ALERT SDA SCL Digital Output Analog Input Analog Input Analog input Analog Input Analog Output Digital Output Digital I/O Digital Input Open-Drain Digital Output. This output is asserted (low) when either of the fans stall or fail to spin up. Cathode Connection to Thermal Diode 1. Anode Connection to Thermal Diode 1. 0 V to 2.25 V Analog Input. Can be reconfigured as thermistor input or as a cathode connection to Thermal Diode 2. Configured for thermistor connection by default. 0 V to 2.25 V Analog Input. Can be reconfigured as thermistor input or as an anode connection to Thermal Diode 2. Configured for thermistor connection by default. 2.25 V Reference Voltage Output, 20 mA maximum output current. Open-Drain Digital Output. The SMBus ALERT pin alerts the system to out-of-limit events such as a failed fan, overtemperature, or out-of-limit analog measurement. Open-Drain Digital I/O. SMBus bidirectional serial data. Requires SMBus pull-up resistor. Open-Drain Digital Input. SMBus serial clock input. Requires SMBus pull-up resistor.
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ADT7466 TYPICAL PERFORMANCE CHARACTERISTICS
20 10 D+ TO GND
TEMPERATURE ERROR (C)
0 -10 DEVICE 1
TEMPERATURE ERROR (C)
DEVICE 2
0 -10 -20 D+ TO VCC -30 -40
04711-004
-20 -30 DEVICE 3 -40 -50 -60 -70 0 5 10 15 CAPACITANCE (nF) 20 25
-60 0 20 40 60 LEAKAGE RESISTANCE (M) 80
100
Figure 4. Temperature Error vs. PCB Track Resistance
20
Figure 7. Temperature Error vs. Capacitance Between D+ and D-
40 35
15
TEMPERATURE ERROR (C) TEMPERATURE ERROR (C)
100mV 30 25 20 15 10 60mV 5 0 40mV -5 0 1 2 3 4 NOISE FREQUENCY (MHz) 5 6
04711-008
10
5
100mV
0 250mV
04711-005
-5
-10 0 1 2 3 4 NOISE FREQUENCY (MHz) 5 6
Figure 5. Remote Temperature Error vs. Power Supply Noise Frequency
35 30 25
TEMPERATURE ERROR (C)
Figure 8. Remote Temperature Error vs. Common-Mode Noise Frequency
90 80 70
TEMPERATURE ERROR (C)
20 15 10 5 0 -5 100mV -10
04711-006
60 50 40 30 20 10 0 -10 0 1 2 3 4 NOISE FREQUENCY (MHz) 40mV 5 6
04711-009
250mV
100mV
60mV
-15 -20 0 1 2 3 4 NOISE FREQUENCY (MHz) 5 6
Figure 6. Local Temperature Error vs. Power Supply Noise Frequency
Figure 9. Remote Temperature Error vs. Differential Mode Noise Frequency
Rev. 3 | Page 8 of 48 | www.onsemi.com
04711-007
-50
ADT7466
7 6 DEVICE 1 5 4 DEVICE 3 3 2 1 0 3.0 3.2 140 EXTERNAL 120
MEASURED TEMPERATURE (C)
DEVICE 2
100 INTERNAL 80 60 40 20 0 0 10 20 30 TIME (s) 40 50 60
IDD (A)
3.4
3.6
3.8 4.0
4.2 4.4 VDD (V)
4.6 4.8
5.0
5.2
5.4
Figure 10. Standby Supply Current vs. Supply Voltage
16 14 DEVICE 1 12 1.00 0.99 0.98
Figure 13. Response to Thermal Shock
DEVICE 3 0.97 0.96
SHUTDOWN IDD (A)
10
IDD (mA)
0.95 DEVICE 1 0.94 0.93
8 DEVICE 3 6 DEVICE 2 4
04711-011
0.92 0.91 0.90 0.89 3.0 3.2 3.4 3.6 3.8 4.0 4.2 4.4 VDD (V) 4.6 4.8 5.0 5.2 5.4
04711-013
2 0 0 50 100 150 200 250 SCL FREQUENCY (kHz) 300 350
DEVICE 2
400
Figure 11. Standby Current vs. Clock Frequency
120 100 80 60 40 20 0
04711-014
Figure 14. Supply Current vs. Supply Voltage
2 1 0 -1 MEAN -2 -3 -4
04711-015
HIGH SPEC
PENTIUM 4 READING (C)
-20 -40 -40
TEMPERATURE ERROR
-5 LOW SPEC -6 -40 0 20 40 60 85 TEMPERATURE (C) 105 125
-20
0
20 40 60 80 ACTUAL TEMPERATURE (C)
100
120
Figure 12. Pentium 4 Temperature Measurement vs. ADT7466 Reading
Figure 15. Local Temperature Error
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04711-012
04711-010
ADT7466
2 1 HIGH SPEC
TEMPERATURE ERROR
0 -1 MEAN -2 -3 -4 LOW SPEC -5 -40 0 20 40 60 85 TEMPERATURE (C) 105 125
Figure 16. Remote Temperature Error
Rev. 3 | Page 10 of 48 | www.onsemi.com
04711-016
ADT7466 FUNCTIONAL DESCRIPTION
The ADT7466 is a complete thermal monitor and dual fan controller for any system requiring monitoring and cooling. The device communicates with the system via a serial system management bus (SMBus). The serial data line (SDA, Pin 15) is used for reading and writing addresses and data. The input line, (SCL, Pin 16) is the serial clock. All control and programming functions of the ADT7466 are performed over the serial bus. In addition, an ALERT output is provided to indicate out-of-limit conditions. The device also accepts input from an on-chip band gap temperature sensor that monitors system ambient temperature. Power is supplied to the chip via Pin 6. The system also monitors VCC through this pin. It is normally connected to a 3.3 V supply. It can, however, be connected to a 5 V supply and monitored without going over range.
SEQUENTIAL MEASUREMENT
When the ADT7466 monitoring sequence is started, it sequentially cycles through the measurement of analog inputs and the temperature sensors. Measured values from these inputs are stored in value registers, which can be read out over the serial bus, or can be compared with programmed limits stored in the limit registers. The results of out of limit comparisons are stored in the status registers, which can be read over the serial bus to flag out-of-limit conditions.
MEASUREMENT INPUTS
The device has three measurement inputs, two for voltage and one for temperature. It can also measure its own supply voltage and can measure ambient temperature with its on-chip temperature sensor. Pin 11 and Pin 12 are analog inputs with an input range of 0 V to 2.25 V. They can easily be scaled for other input ranges by using external attenuators. These pins can also be configured for temperature monitoring by using thermistors or a second remote diode temperature measurement. The ADT7466 can simultaneously monitor the local temperature, the remote temperature by using a discrete transistor, and two thermistor temperatures. Remote temperature sensing is provided by the D+ and D- inputs, to which diode connected, remote temperature sensing transistors such as a 2N3904 or CPU thermal diode can be connected. Temperature sensing using thermistors is carried out by placing the thermistor in series with a resistor. The excitation voltage is provided by the REFOUT pin. Table 4. Internal Register Summary
Register Configuration Address Pointer Status Interrupt Mask Value and Limit Offset PROCHOT Status TMIN TRANGE Enhance Acoustics
FAN SPEED MEASUREMENT AND CONTROL
The ADT7466 has two tachometer inputs for measuring the speed of 3-wire fans, and it has two 8-bit DACs to control the speed of two fans. The temperature measurement and fan speed control can be linked in an automatic control loop, which can operate without CPU intervention to maintain system operating temperature within acceptable limits. The enhanced acoustics feature ensures that fans operate at the minimum possible speed consistent with temperature control, and change speed gradually. This reduces the user's perception of changing fan speed.
INTERNAL REGISTERS OF THE ADT7466
Table 4 provides brief descriptions of the ADT7466's principal internal registers. More detailed information on the function of each register is given in Table 30 to Table 72.
Description These registers provide control and configuration of the ADT7466 including alternate pinout functionality. This register contains the address that selects one of the other internal registers. When writing to the ADT7466, the first byte of data is always a register address, which is written to the address pointer register. These registers provide status of each limit comparison and are used to signal out-of-limit conditions on the temperature, voltage, or fan speed channels. Whenever a status bit is set, the ALERT output (Pin 14) goes low. These registers allow interrupt sources to be masked so that they do not affect the ALERT output. The results of analog voltage inputs, temperature, and fan speed measurements are stored in these registers, along with their limit values. These registers allow each temperature channel reading to be offset by a twos complement value written to these registers. This register allows the ADT7466 to monitor and time any PROCHOT events gauging system performance. These registers program the starting temperature for each fan under automatic fan speed control. These registers program the temperature-to-fan speed control slope in automatic fan speed control mode for each fan drive output. This register sets the step size for fan drive changes in AFC mode to minimize acoustic noise.
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ADT7466 THEORY OF OPERATION
SERIAL BUS INTERFACE
The serial system management bus (SMBus) is used to control the ADT7466. The ADT7466 is connected to this bus as a slave device under the control of a master controller. The ADT7466 has an SMBus timeout feature. When this is enabled, the SMBus times out after typically 25 ms of no activity. However, this feature is enabled by default. Bit 5 of Configuration Register 1 (0x00) should be set to 1 to disable this feature. The ADT7466 supports optional packet error checking (PEC). It is triggered by supplying the extra clock pulses for the PEC byte. The PEC byte is calculated using CRC-8. The frame check sequence (FCS) conforms to CRC-8 by the polynomial
C ( x ) = x 8 + x 2 + x1 + 1
may be interpreted as a stop signal. The number of data bytes that can be transmitted over the serial bus in a single read or write operation is limited only by what the master and slave devices can handle. When all data bytes have been read or written, stop conditions are established. In write mode, the master pulls the data line high during the 10th clock pulse to assert a stop condition. In read mode, the master device overrides the acknowledge bit by pulling the data line high during the low period before the ninth clock pulse. This is known as No Acknowledge. The master takes the data line low during the low period before the 10th clock pulse, and then high during the 10th clock pulse to assert a stop condition. Any number of bytes of data can be transferred over the serial bus in one operation, but it is not possible to mix read and write in one operation, because the type of operation is determined at the beginning and subsequently cannot be changed without starting a new operation. ADT7466 write operations contain either one or two bytes, and read operations contain one byte, and perform the following functions. To write data to one of the device data registers or read data from it, the address pointer register must be set so that the correct data register is addressed, and data can be written to that register or read from it. The first byte of a write operation always contains an address that is stored in the address pointer register. If data is to be written to the device, the write operation contains a second data byte that is written to the register selected by the address pointer register. This is shown in Figure 17. The device address is sent over the bus followed by R/W set to 0. This is followed by two data bytes. The first data byte is the address of the internal data register to be written to, which is stored in the address pointer register. The second data byte is the data to be written to the internal data register. When reading data from a register, there are two possibilities. If the ADT7466 address pointer register value is unknown or not the desired value, it is necessary to first set it to the correct value before data can be read from the desired data register. This is done by performing a write to the ADT7466 as before, but only the data byte containing the register address is sent since data is not to be written to the register. This is shown in Figure 18. A read operation is then performed consisting of the serial bus address, R/W bit set to 1, followed by the data byte read from the data register. This is shown in Figure 19.
Consult the SMBus Specifications Rev. 1.1 for more information (www.smbus.org). The ADT7466 has a 7-bit serial bus address, which is fixed at 1001100. The serial bus protocol operates as follows: The master initiates data transfer by establishing a start condition, defined as a high-to-low transition on the serial data line SDA while the serial clock line SCL remains high. This indicates that an address/data stream follows. All slave peripherals connected to the serial bus respond to the start condition, and shift in the next 8 bits, consisting of a 7-bit address (MSB first) and a R/W bit, which determines the direction of the data transfer, that is, whether data is written to or read from the slave device. The address of the ADT7466 is set at 1001100. Since the address must always be followed by a write bit (0) or a read bit (1), and data is generally handled in 8-bit bytes, it may be more convenient to think that the ADT7466 has an 8-bit write address of 10011000 (0x98) and an 8-bit read address of 10011001 (0x99). The peripheral whose address corresponds to the transmitted address responds by pulling the data line low during the low period before the 9th clock pulse, known as the acknowledge bit. All other devices on the bus now remain idle while the selected device waits for data to be read from or written to it. If the R/W bit is 0, the master writes to the slave device. If the R/W bit is 1, the master reads from the slave device. Data is sent over the serial bus in sequences of 9 clock pulses, 8 bits of data followed by an acknowledge bit from the slave device. Transitions on the data line must occur during the low period of the clock signal and remain stable during the high period, because a low-to-high transition when the clock is high
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ADT7466
If the address pointer register is known to already be at the desired address, data can be read from the corresponding data register without first writing to the address pointer register, so the procedure in Figure 18 can be omitted.
1 SCL 9 1 9
SDA START BY MASTER
1
0
0
1
1
0
0
R/W ACK. BY ADT7466
D7
D6
D5
D4
D3
D2
D1
D0 ACK. BY ADT7466
FRAME 1 SERIAL BUS ADDRESS BYTE 1 SCL (CONTINUED)
FRAME 2 ADDRESS POINTER REGISTER BYTE 9
SDA (CONTINUED)
D7
D6
D5
D4
D3
D2
D1
D0 ACK. BY ADT7466 STOP BY MASTER
04711-017
FRAME 3 DATA BYTE
Figure 17. Writing a Register Address to the Address Pointer Register, then Writing Data to the Selected Register
1 SCL
9
1
9
SDA START BY MASTER
1
0
0
1
1
0
0
R/W ACK. BY ADT7466
D7
D6
D5
D4
D3
D2
D1
D0
04711-018 04711-019
ACK. BY ADT7466 FRAME 2 ADDRESS POINTER REGISTER BYTE
STOP BY MASTER
FRAME 1 SERIAL BUS ADDRESS BYTE
Figure 18. Writing to the Address Pointer Register Only
1 SCL
9
1
9
SDA START BY MASTER
1
0
0
1
1
0
0
R/W ACK. BY ADT7466
D7
D6
D5
D4
D3
D2
D1
D0 NO ACK. BY STOP BY MASTER MASTER
FRAME 1 SERIAL BUS ADDRESS BYTE
FRAME 2 ADDRESS POINTER REGISTER BYTE
Figure 19. Reading Data from a Previously Selected Register
Although it is possible to read a data byte from a data register without first writing to the address pointer register if the address pointer register is already at the correct value, it is not possible to write data to a register without writing to the address pointer register, because the first data byte of a write is always written to the address pointer register.
In addition to supporting the send byte and receive byte protocols, the ADT7466 also supports the read byte protocol (see the SMBus Specifications Rev. 1.1 for more information). If it is required to perform several read or write operations in succession, the master can send a repeat start condition instead of a stop condition to begin a new operation.
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ADT7466
WRITE AND READ OPERATIONS
The SMBus specification defines several protocols for different types of write and read operations. The protocols used in the ADT7466 are discussed in the following sections. The following abbreviations are used in the diagrams: S--Start P--Stop R--Read W--Write A--Acknowledge A--No Acknowledge 3. 4. 5. 6. 7. 8. The addressed slave device asserts ACK on SDA. The master sends a register address. The slave asserts ACK on SDA. The master sends a data byte. The slave asserts ACK on SDA. The master asserts a stop condition on SDA to end the transaction.
This is shown in Figure 21.
1 S 2 3 4 REGISTER ADDRESS 5 6 78
04711-021 04711-022
Write Operations
The ADT7466 uses the send byte and write byte protocols.
SLAVE WA ADDRESS
A DATA A P
Send Byte
In this operation, the master device sends a single command byte to a slave device, as follows: 1. 2. The master device asserts a start condition on SDA. The master sends the 7-bit slave address followed by the write bit (low). The addressed slave device asserts ACK on SDA. The master sends a register address. The slave asserts ACK on SDA. The master asserts a stop condition on SDA and the transaction ends. 3. For the ADT7466, the send byte protocol is used to write a register address to RAM for a subsequent single-byte read from the same address. This is shown in Figure 20.
1 S 2 SLAVE ADDRESS W 3 A 4 REGISTER ADDRESS 5 A 6 P
04711-020
Figure 21. Single-Byte Write to a Register
Read Operations
The ADT7466 uses the following SMBus read protocols.
Receive Byte
This is useful when repeatedly reading a single register. The register address needs to have been set up previously. In this operation, the master device receives a single byte from a slave device, as follows: 1. 2. The master device asserts a start condition on SDA. The master sends the 7-bit slave address followed by the read bit (high). The addressed slave device asserts ACK on SDA. The master receives a data byte. The master asserts NO ACK on SDA. The master asserts a stop condition on SDA and the transaction ends.
3. 4. 5. 6.
4. 5. 6.
Figure 20. Setting a Register Address for Subsequent Read
If it is required to read data from the register immediately after setting up the address, the master can assert a repeat start condition immediately after the final ACK and carry out a singlebyte read without asserting an intermediate stop condition.
For the ADT7466, the receive byte protocol is used to read a single byte of data from a register whose address was set previously by a send byte or write byte operation.
1 S 2 SLAVE ADDRESS R 3 A 4 DATA 5 A 6 P
Write Byte
In this operation, the master device sends a command byte and one data byte to the slave device, as follows: 1. 2. The master device asserts a start condition on SDA. The master sends the 7-bit slave address followed by the write bit (low).
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Figure 22. Single-Byte Read from a Register
ADT7466
ALERT RESPONSE ADDRESS (ARA)
ARA is a feature of SMBus devices that allows an interrupting device to identify itself to the host when multiple devices exist on the same bus. The ALERT output can be used as an interrupt output, or it can be used as an ALERT. One or more outputs can be connected to a common ALERT line connected to the master. If a device's ALERT line goes low, the following occurs: 1. 2. ALERT is pulled low. The master initiates a read operation and sends the alert response address (ARA = 0001 100). This is a general call address, which must not be used as a specific device address. The device whose ALERT output is low responds to the alert response address, and the master reads its device address. The address of the device is now known, and it can be interrogated in the usual way. 4. If more than one device's ALERT output is low, the one with the lowest device address has priority, in accordance with normal SMBus arbitration. 5. Once the ADT7466 responds to the alert response address, the master must read the status registers, the ALERT is cleared only if the error condition no longer exists. Associated with each voltage measurement channel are high and low limit registers. Exceeding the programmed high or low limit causes the appropriate status bit to be set. Exceeding either limit can also generate ALERT interrupts. of 10 bits. The basic input range is 0 V to 2.25 V, but the VCC input has built in attenuators to allow measurement of 3.3 V or 5 V. To allow for the tolerance of the supply voltage, the ADC produces an output of 3/4 full scale (decimal 768 or 0x300) for the nominal supply voltage, and so has adequate headroom to cope with overvoltages. Table 9 shows the input ranges of the analog inputs and the output codes of the ADC.
Table 6. Voltage Measurement Registers
Register 0x0A 0x0B 0x0C Description AIN1 reading AIN2 reading VCC reading Default 0x00 0x00 0x00
3.
Table 7. Voltage Measurement Limit Registers
Register 0x14 0x15 0x16 0x17 0x18 0x19 Description AIN1 low limit AIN1 high limit AIN2 low limit AIN2 high limit VCC low limit VCC high limit Default 0x00 0xFF 0x00 0xFF 0x00 0xFF
SMBus TIMEOUT
The ADT7466 includes an SMBus timeout feature. If there is no SMBus activity for 25 ms, the ADT7466 assumes that the bus is locked, and it releases the bus. This prevents the device from locking or holding the SMBus expecting data. Some SMBus controllers cannot handle the SMBus timeout feature, so they are disabled.
When the ADC is running, it samples and converts a voltage input in 1 ms, and averages 16 conversions to reduce noise. Therefore a measurement on each input takes nominally 16 ms.
Turn Off Averaging
For each voltage measurement read from a value register, 16 readings have actually been made internally and the results averaged, before being placed into the value register. There can be an instance where faster conversions are required. Setting Bit 4 of Configuration Register 2 (0x01) turns averaging off. This effectively gives a reading 16 times faster (1 ms), but as a result the reading can be noisier.
Table 5. Configuration Register 1--Register 0x00
Bit Address and Value <5> TODIS = 0 <5> TODIS = 1 Description SMBus timeout enabled (default) SMBus timeout disabled
VOLTAGE MEASUREMENT
The ADT7466 has two external voltage measurement channels. Pin 11 and Pin 12 are analog inputs with a range of 0 V to 2.25 V. It can also measure its own supply voltage, VCC. The VCC supply voltage measurement is carried out through the VCC pin (Pin 6). Setting Bit 6 of Configuration Register 1 (0x00) allows a 5 V supply to power the ADT7466 and be measured without overranging the VCC measurement channel.
Single-Channel ADC Conversions
Setting Bit 3 of Configuration Register 4 (0x03) places the ADT7466 into single-channel ADC conversion mode. In this mode, the ADT7466 can be made to read a single voltage channel only. If the internal ADT7466 clock is used, the selected input is read every 1 ms. The appropriate ADC channel is selected by writing to Bits 2:0 of Configuration Register 4 (0x03).
A/D Converter All analog inputs are multiplexed into the on-chip, successive approximation, analog-to-digital converter. This has a resolution
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ADT7466
Table 8. Single-Channel ADC Conversions
Bits 2:0, Reg. 0x03 000 001 010 Channel Selected AIN1 AIN2 VCC
REFERENCE VOLTAGE OUTPUT
The ADT7466 has a reference voltage of 2.25 V, which is available on Pin 13 of the device. It can be used for scaling and offsetting the analog inputs to give different voltage ranges. It can also be used as an excitation voltage for a thermistor when the analog inputs are configured as thermistor inputs. See the Temperature Measurement section for more details.
CONFIGURATION OF PIN 11 AND PIN 12
Pin 11 and Pin 12 can be used for analog inputs, thermistor inputs, or connecting a second remote thermal diode. The
ADT7466 is configured for thermistor connection by default. The device is configured for the different modes by setting the appropriate bits in the configuration registers. Bits 6:7 of Configuration Register 3 (0x02) configure the device for either analog inputs or thermistor inputs. Bit 7 of Configuration Register 2 (0x01) configures Pin 11 and Pin 12 for the connection of a second thermal diode. Bits 2:3 of Interrupt Status Register 2 (0x11) indicate either an open or short circuit on Thermal Diode 1 and Diode 2 inputs. Bits 4:5 of Interrupt Status Register 2 (0x11) indicate either an open or short circuit on TH1 and TH2 inputs. It is advisable to mask interrupts on diode open/short alerts when in thermistor monitoring mode and to mask interrupts on thermistor open/short alerts when in REM2 mode.
Table 9. A-to-D Output Code vs. VIN
VCC 3.3 V <0.0172 0.017-0.034 0.034-0.052 0.052-0.069 1.110-1.127 2.220-2.237 3.3-3.347 4.371-4.388 4.388-4.405 4.405-4.423 >4.423 VCC 5 V <0.026 0.026-0.052 0.052-0.078 0.078-0.104 1.667-1.693 3.333-3.359 5-5.026 6.563-6.589 6.589-6.615 6.615-6.641 >6.634 AIN <0.0088 0.0088-0.0176 0.0176-0.0264 0.0264-0.0352 0.563-0.572 1.126-1.135 1.689-1.698 2.218-2.226 2.226-2.235 2.235-2.244 >2.244 Decimal 0 1 2 3 64 (1/4 scale) 128 (1/2 scale) 192 (3/4 scale) 252 253 254 255 Binary 00000000 00000001 00000010 00000011 01000000 10000000 11000000 11111100 11111101 11111110 11111111
Table 10. Mode Configuration Summary
Mode Thermistor Mode TH1 TH2 AIN Mode AIN1 AIN2 Remote 2 Diode Mode Register 0x 02 Bit 7 = 0 Register 0x02 Bit 6 = 0 Register 0x01 Bit 7 = 1 Low: Reg 0x14 High: Reg 0x15 Low: Reg 0x16 High: Reg 0x17 Low: Reg 0x14 High: Reg 0x15 OOL: Reg. 0x10, Bit 6 OOL: Reg. 0x10, Bit 5 OOL: Reg. 0x10, Bit 6 NC: Reg. 0x11, Bit 3 Mask interrupts on thermistor NC. (Set Bits 4:5 of Reg. 0x13) and AIN2 (Bit 5 of Reg. 0x12.) Configuration Register Settings Limits Alerts1 Description Default mode. Mask interrupts on diode NC. (Set Bits 2:3 of Reg. 0x13.)
Register 0x02 Bit 7 = 1 Register 0x02 Bit 6 = 1
Low: Reg 0x14 High: Reg 0x15 Low: Reg 0x16 High: Reg 0x17
OOL: Reg. 0x10, Bit 6 NC: Reg. 0x11, Bit 4 OOL: Reg. 0x10, Bit 5 NC: Reg. 0x11, Bit 5 Ensure that AFC is not on. (Clear Bits 0:1 of AFC Configuration Register 1, 0x05.)
1
OOL = Out of limit. NC = No connection.
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ADT7466
TEMPERATURE MEASUREMENT
The ADT7466 has two dedicated temperature measurement channels, one for measuring the temperature of an on-chip band gap temperature sensor, and one for measuring the temperature of a remote diode, usually located in the CPU. In addition, the analog input channels, AIN1 and AIN2, can be reconfigured to measure the temperature of a second diode by setting Bit 7 of Configuration Register 2 (0x01), or to measure temperature using thermistors by setting Bit 6 and/or Bit 7 of Configuration Register 3 (0x02). collector is not grounded, and should be linked to the base. To prevent ground noise from interfering with the measurement, the more negative terminal of the sensor is not referenced to ground but is biased above ground by an internal diode at the D- input. If the sensor is operating in an extremely noisy environment, C1 may optionally be added as a noise filter. Its value should never exceed 1000 pF. See the Layout Considerations section for more information on C1. To measure VBE, the operating current through the sensor is switched between three related currents. Figure 24 shows N1 x I and N2 x I as different multiples of the current I. The currents through the temperature diode are switched between I and N1 x I, giving VBE1, and then between I and N2 x I, giving VBE2. The temperature can then be calculated using the two VBE measurements. This method can also cancel the effect of series resistance on the temperature measurement. The resulting VBE waveforms are passed through a 65 kHz low-pass filter to remove noise, and then to a chopper-stabilized amplifier. This amplifies and rectifies the waveform to produce a dc voltage proportional to VBE. The ADC digitizes this voltage, and a temperature measurement is produced. To reduce the effects of noise, digital filtering is performed by averaging the results of 16 measurement cycles for low conversion rates. Signal conditioning and measurement of the internal temperature sensor is performed in the same manner.
SERIES RESISTANCE CANCELLATION
Parasitic resistance, seen in series with the remote diode between the D+ and D- inputs to the ADT7466, is caused by a variety of factors including PCB track resistance and track length. This series resistance appears as a temperature offset in the sensor's temperature measurement. This error typically causes a 1C offset per ohm of parasitic resistance in series with the remote diode. The ADT7466 automatically cancels the effect of this series resistance on the temperature reading, giving a more accurate result without the need for user characterization of the resistance. The ADT7466 is designed to automatically cancel typically 2 k of resistance. This is done transparently to the user, using an advanced temperature measurement method described in the following section.
TEMPERATURE MEASUREMENT METHOD
A simple method of measuring temperature is to exploit the negative temperature coefficient of a diode, by measuring the base emitter voltage (VBE) of a transistor operated at constant current. Unfortunately, this technique requires calibration to null out the effect of the absolute value of VBE, which varies from device to device. The technique used in the ADT7466 measures the change in VBE when the device is operated at three different currents. Previous devices used only two operating currents, but it is the third current that allows series resistance cancellation. Figure 24 shows the input signal conditioning used to measure the output of a remote temperature sensor. This figure shows the remote sensor as a substrate transistor, provided for temperature monitoring on some microprocessors, but it could also be a discrete transistor. If a discrete transistor is used, the
USING DISCRETE TRANSISTORS
If a discrete transistor is used, the collector is not grounded and should be linked to the base. If an NPN transistor is used, the emitter is connected to the D- input and the base to the D+ input. If a PNP transistor is used, the base is connected to the D- input and the emitter to the D+ input. Figure 23 shows how to connect the ADT7466 to an NPN or PNP transistor for temperature measurement. To prevent ground noise interfering with the measurement, the more negative terminal of the sensor is not referenced to ground, but is biased above ground by an internal diode at the D- input.
ADT7466
2N3904 NPN D+ D- 2N3906 PNP
ADT7466
D+ D-
04711-023
Figure 23. Connections for NPN and PNP Transistors
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ADT7466
VDD I N1 x I N2 x I IBIAS
D+ REMOTE SENSING TRANSISTOR C1* D- BIAS DIODE
VOUT+ TO ADC VOUT- LOW-PASS FILTER fC = 65kHz
04711-024
*CAPACITOR C1 IS OPTIONAL. IT SHOULD ONLY BE USED IN NOISY ENVIRONMENTS.
Figure 24. Signal Conditioning for Remote Diode Temperature Sensors
Temperature Data Format
The temperature data stored in the temperature data registers consists of a high byte with an LSB size equal to 1C. If higher resolution is required, two additional bits are stored in the extended temperature registers, giving a resolution of 0.25C. The temperature measurement range for both local and remote measurements is, by default, 0C to 127C (binary), so the ADC output code equals the temperature in degrees Celsius, and half the range of the ADC is not actually used. The ADT7466 can also be operated by using an extended temperature range from -64C to +191C. In this case, the whole range of the ADC is used, but the ADC code is offset by +64C, so it does not correspond directly to the temperature. (0C = 0100000) . The user can switch between these two temperature ranges by setting or clearing Bit 7 in Configuration Register 1. The measurement range should be switched only once after powerup, and the user should wait for two monitoring cycles (approximately 68 ms) before expecting a valid result. Both ranges have different data formats, as shown in Table 11.
greater than those specified in the Absolute Maximum Ratings table. Furthermore, the device is guaranteed to only operate at ambient temperatures from -40C to +125C. In practice, the device itself should not be exposed to extreme temperatures, and may need to be shielded in extreme environments to comply with these requirements. Only the remote temperature monitoring diode should be exposed to temperatures above +120C and below -40C. Care should be taken in choosing a remote temperature diode to ensure that it can function over the required temperature range.
Nulling Out Temperature Errors
The ADT7466 automatically nulls out temperature measurement errors due to series resistance, but systematic errors in the temperature measurement can arise from a number of sources, and the ADT7466 can reduce these errors. As CPUs run faster, it is more difficult to avoid high frequency clocks when routing the D+, D- tracks around a system board. Even when recommended layout guidelines are followed, there may still be temperature errors attributed to noise being coupled onto the D+/D- lines. High frequency noise generally has the effect of giving temperature measurements that are too high by a constant amount. The ADT7466 has temperature offset registers at addresses 0x26 and 0x27 for the remote and local temperature channels. A one time calibration of the system can determine the offset caused by system board noise and null it out using the offset registers. The offset registers automatically add a twos complement 8-bit reading to every temperature measurement. The LSB adds 1C offset to the temperature reading so the 8-bit register effectively allows temperature offsets of up to 128C with a resolution of 1C. This ensures that the readings in the temperature measurement registers are as accurate as possible.
Table 11. Temperature Data Format
Temperature -64C 0C 1C 10C 25C 50C 75C 100C 125C 127C 191C
1
Binary1 0 000 0000 0 000 0000 0 000 0001 0 000 1010 0 001 1001 0 011 0010 0 100 1011 0 110 0100 0 111 1101 0 111 1111 0 111 1111
Offset Binary2 0 000 0000 0 100 0000 0 100 0001 0 100 1010 0 101 1001 0 111 0010 1 000 1011 1 010 0100 1 011 1101 1 011 1111 1 111 1111
Table 12. Temperature Offset Registers
Register 0x24 0x25 0x26 0x27 Description Thermistor 1/Remote 2 offset Thermistor 2 offset Remote1 temperature offset Local temperature offset Default 0x00 (0C) 0x00 (0C) 0x00 (0C) 0x00 (0C)
Binary scale temperature measurement returns 0 for all temperatures 0C. 2 Offset binary scale temperature values are offset by +64.
While the temperature measurement range can be set to -64C to +191C for both local and remote temperature monitoring, the ADT7466 itself should not be exposed to temperatures
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ADT7466
Table 13. Temperature Measurement Registers
Register 0x0D 0x0E 0x08 0x09 Description Remote temperature Local temperature Extended Resolution 1 Bits 1:0 remote temperature LSBs Extended Resolution 2 Bits 1:0 local temperature LSBs Default 0x00 0x00 0x00 0x00
measurement. When using long cables, the filter capacitor could be reduced or removed. Route the D+ and D- tracks close together, in parallel, with grounded guard tracks on each side. Provide a ground plane under the tracks if possible. Use wide tracks to minimize inductance and reduce noise pickup. A 5 mil track minimum width and spacing is recommended.
GND 5MIL 5MIL D+ 5MIL 5MIL
Associated with each temperature measurement channel are high and low limit registers. Exceeding the programmed high or low limit causes the appropriate status bit to be set. Exceeding either limit can also generate ALERT interrupts.
Table 14. Temperature Measurement Limit Registers
Register 0x1A 0x1B 0x1C 0x1D 0x14 0x15 0x16 0x17 Description Remote1 temperature low limit Remote1 temperature high limit Local temperature low limit Local temperature high limit Thermistor 1/Remote 2 low limit Thermistor 1/Remote 2 high limit Thermistor 2 low limit Thermistor 2 high limit Default 0x00 0x7F 0x00 0x7F 0x00 0xFF 0x00 0xFF
D-
5MIL
04711-044
5MIL GND 5MIL
Figure 25. Arrangement of Signal Tracks
Try to minimize the number of copper/solder joints, which can cause thermocouple effects. Where copper/solder joints are used, make sure that they are in both the D+ and D- paths and are at the same temperature. Thermocouple effects should not be a major problem because 1C corresponds to about 240 V, and thermocouple voltages are about 3 V/C of temperature difference. Unless there are two thermocouples with a big temperature differential between them, thermocouple voltages should be much less than 200 mV. Place a 0.1 F bypass capacitor close to the ADT7466.
All temperature limits must be programmed in the same format as the temperature measurement. If this is offset binary, add 64 (0x40 or 01000000) to the actual temperature limit in degrees Celsius.
Layout Considerations
Digital boards can be electrically noisy environments. Take the following precautions to protect the analog inputs from noise, particularly when measuring the very small voltages from a remote diode sensor. Place the ADT7466 as close as possible to the remote sensing diode. Provided that the worst noise sources, such as clock generators, data/address buses and CRTs, are avoided, this distance can be 4 inches to 8 inches. If the distance to the remote sensor is more than 8 inches, the use of twisted-pair cable is recommended. This works from about 6 feet to 12 feet. For very long distances (up to 100 feet), use shielded twisted pair, such as Belden #8451 microphone cable. Connect the twisted pair to D+ and D- and the shield to GND close to the ADT7466. Leave the remote end of the shield unconnected to avoid ground loops. Because the measurement technique uses switched current sources, excessive cable and/or filter capacitance can affect the
TEMPERATURE MEASUREMENT USING THERMISTORS
The analog input channels, AIN1 and AIN2, can be used to measure temperature by using negative temperature coefficient (NTC) thermistors. NTC thermistors have a nonlinear transfer function of the form
B B Rt2 = Rt1 x e - t 2 t1
where: Rt2 is the resistance at temperature t2. Rt1 is the resistance at temperature t1 (usually 25C). e = 2.71828. B is the B constant of the thermistor (typically between 3000 and 5000). A thermistor can be made to give a voltage output that is fairly linear over a limited range by making it part of a potential divider as shown in Figure 26.
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ADT7466
A potential divider, with a thermistor as the upper part connected to REFOUT, produces an output voltage that varies nonlinearly in proportion to the inverse of the resistance. By suitable choice of thermistor and fixed resistor, this can be made to approximately cancel the nonlinearity of the thermistor resistance vs. temperature curve, thus giving a fairly linear output voltage with temperature over a limited range. This circuit uses REFOUT as the excitation voltage for both the thermistor and for the ADC, so any variation in REFOUT is cancelled, and the measurement is purely ratiometric.
ADT7466
REFOUT TH2 TH1 TH1 TH2
04711-025
REXT2
REXT1
Figure 26. Temperature Measurement Using Thermistor
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ADT7466
Thermistor Linearization
A linear transfer function can be obtained over a limited temperature range by connecting the thermistor in series with an optimum resistor. Placing a resistor in series with the thermistor as shown in Figure 26 produces an S-shaped error curve as shown in Figure 27. The overall error across the range can be reduced by calculating the external resistor so that the error is 0 at the ends of the range. REXT is calculated as follows:
Thermistor Normalization
Even when the thermistor is linearized, it does not provide an output to the ADC that gives a direct temperature reading in degrees Celsius. The linearized data is proportional to the voltage applied; however, normalization is needed to use the value as a temperature reading. To overcome this problem, when an analog input is configured for use with a thermistor, the output of the ADC is scaled and offset so that it produces the same output (for example, 1 LSB = 0.25C) as from the thermal diode input, when REXT is chosen to linearize the thermistor over 30C to 100C. Normalization can be chosen for 10 k thermistors by setting Bit 0 of Configuration Register 2 (0x01) or for 100 k thermistors by clearing this bit (default setting).
R EXT =
R MID x (R MIN + R MAX ) - (2 x R MIN x R MAX ) (R MIN + R MAX - 2 x R MID )
where: RMIN is the thermistor value at TMIN. RMAX is the thermistor value at TMAX. RMID is the thermistor value at TMIN + TMAX
2
Figure 27 shows the linearity error using a 100 k thermistor with a B value of 3500 and a 14400 resistor. Using the specified thermistor and resistor, the error over a temperature range of 30C to 100C is less than 2C. Other thermistors can be used, but the resistor value is different. A smaller error can be achieved over a narrower temperature range; conversely, a wider temperature range can be used, but the error is greater. In both cases, the optimum resistor value is different.
2
READING TEMPERATURE FROM THE ADT7466
It is important to note that temperature can be read from the ADT7466 as an 8-bit value (with 1C resolution) or as a 10-bit value (with 0.25C resolution). If only 1C resolution is required, the temperature readings can be read at any time and in no particular order. If the 10-bit measurement is required, this involves a 2-register read for each measurement. The extended resolution registers (0x08 and 0x09) should be read first. This causes all temperature reading registers to be frozen until all temperature reading registers have been read. This prevents an MSB reading from being updated while its 2 LSBs are being read and vice versa.
1
ERROR (C)
Measurement Sequence
0
The ADT7466 automatically measures each analog and temperature channel in the following round-robin sequence: 1.
04711-026
-1
AIN1/TH1 AIN2(TH2) VCC Remote Temperature 1 (D1) Local Temperature
2. 3. 4. 5.
-2 30
40
50
60 70 TEMPERATURE (C)
80
90
100
Figure 27. Linearity Error Using Specified Components
If AIN1 and AIN2 are configured for a second thermal diode, this is measured instead of the AIN1 and AIN 2 measurements, and the result stored in the AIN1 reading register (0x0A).
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ADT7466
Analog Monitoring Cycle Time The analog monitoring cycle begins when a 1 is written to the start bit (Bit 0) of Configuration Register 1 (0x00). The ADC measures each analog input in turn, and, as each measurement is completed, the result is automatically stored in the appropriate value register. This round-robin monitoring cycle continues until disabled by writing a 0 to Bit 0 of Configuration Register 1.
Since the ADC is normally left to free-run in this manner, the time to monitor all the analog inputs is normally not of interest, because the most recently measured value of any input can be read at any time. For applications where the monitoring cycle time is important, it can easily be calculated from the measurement times of the individual channels. With averaging turned on, each measurement is taken 16 times and the averaged result is placed in the value register. The worst-case monitoring cycle times for averaging turned on and off is described in Table 15. Fan tach measurements are made in parallel but independently and are not synchronized with the analog measurements. temperature channel only. The selected input is read every 1.4 ms. The appropriate ADC channel is selected by writing to Bits 2:0 of Configuration Register 4 (Address 0x03).
Table 16. ADC Single-Channel Selection
Bits 2:0, Reg. 0x03 000 001 010 011 100 101 Channel Selected AIN1/ Thermistor1 AIN2/ Thermistor2 VCC Remote 1 temperature Local temperature Remote 2 temperature
LIMIT VALUES
High and low limits are associated with each measurement channel on the ADT7466. These limits can form the basis of system status monitoring; a status bit can be set for any out-oflimit condition and detected by polling the device. Alternatively, ALERT interrupts can be generated to flag out-of-limit conditions for a processor or microcontroller. Voltage and temperature limits are only 8-bit values and are compared with the 8 MSBs of the voltage and temperature values.
Table 15. Monitoring Cycle Time
Monitoring Cycle Time Channel Local temperature Remote 1 temperature Remote 2 temperature AIN1/Thermistor 1 AIN2/Thermistor 2 VCC Total1 Total2
1
Avg On 8.99 ms 36.69 ms 36.69 ms 8.65 ms 8.65 ms 8.26ms 71.24 ms 90.63 ms
Avg Off 1.36 ms 6.25 ms 6.25 ms 1.02 ms 1.02 ms 0.61ms 10.26ms 14.47 ms
8-Bit Limits The following tables list the 8-bit limits on the voltage limit and temperature limit registers of the ADT7466.
Table 17. Voltage Limit Registers
Register 0x14 0x15 0x16 0x17 0x18 0x19 Description AIN1 low limit AIN1 high limit AIN2 low limit AIN2 high limit VCC low limit VCC high limit Default 0x00 0xFF 0x00 0xFF 0x00 0xFF
Pin 11 and Pin 12 configured for AIN/thermistor monitoring. The total excludes the Remote 2 temperature time. 2 Pin 11 and Pin 12 configured for second thermal diode monitoring. The total excludes the AIN1/Thermistor 1 and AIN2/Thermistor 2 times.
ADDITIONAL ADC FUNCTIONS
A number of other functions are available on the ADT7466 to offer the systems designer increased flexibility.
Table 18. Temperature Limit Registers
Register 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F 0x20 0x21 0x22 Description Remote temperature low limit Remote temperature high limit Local temperature low limit Local temperature high limit PROCHOT limit AIN1(TH1)/REM2 THERM limit AIN2(TH2) THERM limit Remote THERM limit Local THERM limit Default 0x00 0x7F 0x00 0x7F 0x00 0x64 0x64 0x64 0x64
Turn Off Averaging For each temperature measurement read from a value register, 16 readings have actually been made internally and the results averaged before being placed into the value register. The user may want to take a very fast measurement, for example, of CPU temperature. Setting Bit 4 of Configuration Register 2 (0x01) turns averaging off. Single-Channel ADC Conversions Setting Bit 3 of Configuration Register 4 (Address 0x03) places the ADT7466 into single-channel ADC conversion mode. In this mode, the ADT7466 can be made to read a single
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ADT7466
16-Bit Limits The fan tach measurements are 16-bit results. The fan tach limits are also 16 bits, consisting of a high byte and low byte. Since fans running under speed or stalled are normally the only conditions of interest, only high limits exist for fan tachs. Since the fan tach period is actually being measured, exceeding the limit indicates a slow or stalled fan.
Table 19. Fan Limit Registers
Register 0x4C 0x4D 0x4E 0x4F Description TACH1 minimum low byte TACH1 minimum high byte TACH2 minimum low byte TACH2 minimum high byte Default 0xFF 0xFF 0xFF 0xFF
However, if one of these masked interrupt sources goes out-oflimit, its associated status bit is set in the interrupt status registers.
Table 20. Interrupt Status Register 1 (Reg. 0x10)
Bit No. 7 6 5 4 3 2 1 Name OOL AIN1 AIN2 VCC REM LOC FAN1 FAN2 Description 1 indicates that a bit in Status Register 2 is set and that Status Register 2 should be read. 1 indicates that AIN1 is out of limit. 1 indicates that AIN2 is out of limit. 1 indicates that VCC is out of limit. 1 indicates that the remote temperature measurement is out of limit. 1 indicates that the local temperature measurement is out of limit. 1 indicates that the Tach 1 count is above limit (fan speed below limit). 1 indicates that the Tach 2 count is above limit (fan speed below limit).
Out-of-Limit Comparisons Once all limits have been programmed, ADT7466 monitoring can be enabled. The ADT7466 measures all parameters in roundrobin format and sets the appropriate status bit for out-of-limit conditions. Comparisons are done differently depending on whether the measured value is being compared to a high or low limit.
A greater than comparison is performed when comparing with the high limit. A less than or equal to comparison is performed when comparing with the low limit.
0
Table 21. Interrupt Status Register 2 (Reg. 0x11)
Bit No. 5 4 3 Name THRM2 THRM1 D2 Description 1 indicates that TH1 is open-circuit. 1 indicates that TH2 is open-circuit. 1 indicates that Remote Temperature Sensing Diode 2 is open-circuit or shortcircuit. 1 indicates that Remote Temperature Sensing Diode 1 is open-circuit or shortcircuit. 1 indicates that the PROCHOT limit has been exceeded. 1 indicates that a THERM overtemperature limit has been exceeded.
2
D1
Status Registers The results of limit comparisons are stored in Status Register 1 and Status Register 2. The status register bit for each channel reflects the status of the last measurement and limit comparison on that channel. If a measurement is within limits, the corresponding status register bit is cleared to 0. If the measurement is out-of-limits the corresponding status register bit is set to 1.
The state of the various measurement channels can be polled by reading the status registers over the serial bus. When Bit 7 (OOL) of Status Register 1 (0x10) is 1, an out-of-limit event has been flagged in Status Register 2. Therefore the user need only read Status Register 2 when this bit is set. Alternatively, the ALERT output (Pin 14) can be used as an interrupt, which automatically notifies the system supervisor of an out-of-limit condition. Reading the status registers clears the appropriate status bit as long as the error condition that caused the interrupt has cleared. Status register bits are sticky, meaning that they remain set until read by software. Whenever a status bit is set, indicating an out-of-limit condition, it remains set even if the event that caused it cleared (until read). The only way to clear the status bit is to read the status register when the event clears. Interrupt status mask registers (0x12, 0x13) allow individual interrupt sources to be masked from causing an ALERT.
1 0
PHOT OVT
ALERT INTERRUPT BEHAVIOR
The ADT7466 can be polled for status, or an ALERT interrupt can be generated for out-of-limit conditions. It is important to note how the ALERT output and status bits behave when writing interrupt handler software.
HIGH LIMIT
TEMPERATURE CLEARED ON READ (TEMP BELOW LIMIT) STICKY STATUS BIT TEMP BACK IN LIMIT (STATUS BIT STAYS SET) ALERT
04711-027
Figure 28. ALERT and Status Bit Behavior
Figure 28 shows how the ALERT output and sticky status bits behave. Once a limit is exceeded, the corresponding status bit is
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ADT7466
set to 1. The status bit remains set until the error condition subsides and the status register is read. This ensures that an outof-limit event cannot be missed if software is polling the device periodically. The ALERT output remains low while a reading is out-of-limit, until the status register is read. This has implications on how software handles the interrupt.
Table 22. Interrupt Mask Register 1 (Reg. 0x12)
Bit No. 7 6 5 4 3 2 1 0 Name OOL AIN1(TH1)/ REM2 AIN2(TH2) VCC REM1 LOC FAN1 FAN2 Description 1 masks ALERT for any alert condition flagged in Status Register 2. 1 masks ALERT for AIN1(TH1)/REM2. 1 masks ALERT for AIN2(TH2). 1 masks ALERT for Vcc. 1 masks ALERT for remote temperature. 1 masks ALERT for local temperature. 1 masks ALERT for Fan 1. 1 masks ALERT for Fan 2.
Handling Alert Interrupts To prevent the system from being tied up servicing interrupts, it is recommended to handle the ALERT interrupt as follows:
1. 2. 3. 4. 5. 6. 7. Detect the ALERT assertion. Enter the interrupt handler. Read the status registers to identify the interrupt source. Mask the interrupt source by setting the appropriate mask bit in the interrupt mask registers (0x12, 0x13). Take the appropriate action for a given interrupt source. Exit the interrupt handler. Periodically poll the status registers. If the interrupt status bit has cleared, reset the corresponding interrupt mask bit to 0. This causes the ALERT output and status bits to behave as shown in Figure 29.
HIGH LIMIT
Table 23. Interrupt Mask Register 2 (Reg. 0x13)
Bit No. 5 4 3 2 1 0 Name Description THRM2 1 masks ALERT for TH1 open- or short-circuit errors. THRM1 1 masks TH2 open- or short-circuit errors. D1 1 masks ALERT for Diode 1 open- or shortcircuit errors. D2 1 masks ALERT for Diode 2 open- or shortcircuit errors. PHOT 1 masks ALERT for PROCHOT. OVT 1 masks ALERT for over temperature (exceeding THERM limits).
TEMPERATURE CLEARED ON READ (TEMP BELOW LIMIT) STICKY STATUS BIT ALERT INTERRUPT MASK BIT SET INTERRUPT MASK BIT CLEARED (ALERT REARMED)
04711-028
Measuring PROCHOT Assertion Time
The ADT7466 has an internal timer to measure PROCHOT assertion time. The timer is started on the assertion of the ADT7466 PROCHOT input, and stopped on the negation of the pin. The timer counts PROCHOT times cumulatively, that is, the timer resumes counting on the next PROCHOT assertion. The PROCHOT timer continues to accumulate PROCHOT assertion times until the timer is read (it is cleared on read) or until it reaches full scale. If the counter reaches full scale, it stops at that reading until it is cleared. The 8-bit PROCHOT timer register (0x0F) is designed such that Bit 0 is set to 1 on the first PROCHOT assertion. Once the cumulative PROCHOT assertion time exceeds 50 ms, Bit 1 of the PROCHOT timer is set, and Bit 0 becomes the LSB of the timer with a resolution of 22.76 ms.
TEMP BACK IN LIMIT (STATUS BIT STAYS SET)
Figure 29. How Masking the Interrupt Source Affects ALERT Output
Masking Interrupt Sources Interrupt Mask Registers 1 and 2 are located at Addresses 0x12 and 0x13. These registers allow individual interrupt sources to be masked to prevent ALERT interrupts. Masking an interrupt source prevents only the ALERT output from being asserted; the appropriate status bit is set as normal.
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ADT7466
PROCHOT
PROCHOT limit register. This 8-bit register allows a limit from 0 seconds (first PROCHOT assertion) to 6.4 seconds to be set
00000001 7 6 5 4 3 2 1 0 PROCHOT ASSERTED < OR = 25ms
PROCHOT TIMER (REG. 0x0F)
before an ALERT is generated. The PROCHOT timer value is compared with the contents of the PROCHOT limit register. If the PROCHOT timer value exceeds the PROCHOT limit value, the PHOT bit (Bit 1) of Status Register 2 is set, and an ALERT is generated. The PHOT bit (Bit 1) of Mask Register 2 (0x13) masks ALERTs if this bit is set to 1, although the PHOT bit of Interrupt Status Register 2 is still set if the PROCHOT limit is exceeded. Figure 32 is a functional block diagram of the PROCHOT timer limit and associated circuitry. Writing a value of 0x00 to the PROCHOT limit register (0x21) causes ALERT to be generated on the first PROCHOT assertion. A PROCHOT limit value of 0x01 generates an ALERT when cumulative PROCHOT assertions exceed 50 ms.
PROCHOT
ACCUMULATE PROCHOT LOW ASSERTION TIMES PROCHOT TIMER (REG. 0x0F) 00000010 7 6 5 4 3 2 1 0 PROCHOT ASSERTED > OR = 50ms
PROCHOT
ACCUMULATE PROCHOT LOW ASSERTION TIMES
04711-029
PROCHOT TIMER (REG. 0x0F)
00000101 7 6 5 4 3 2 1 0 PROCHOT ASSERTED > OR = 125ms (100ms + 25ms)
Figure 30. PROCHOT Timer
Figure 30 shows how the PROCHOT timer behaves as the PROCHOT input is asserted and negated. Bit 0 is set on the first PROCHOT assertion that is detected. This bit remains set until the cumulative PROCHOT assertions exceed 50 ms. At this time, Bit 1 of the PROCHOT timer is set, and Bit 0 is cleared. Bit 0 now reflects timer readings with a resolution of 25 ms. When using the PROCHOT timer, be aware of the following. After a PROCHOT timer read (0x0F):
* *
The contents of the timer are cleared on read. The PHOT bit (Bit 1) of Status Register 2 is cleared automatically.
If the PROCHOT timer is read during a PROCHOT assertion, the following happens:
* * * *
The contents of the timer are cleared. Bit 0 of the PROCHOT timer is set to 1 (since a PROCHOT assertion is occurring). The PROCHOT timer increments from 0. If the PROCHOT limit (0x1E) = 0x00, the PHOT bit is set.
Generating ALERT Interrupts from PROCHOT Events
The ADT7466 can generate ALERTs when a programmable PROCHOT limit is exceeded. This allows the systems designer to ignore brief, infrequent PROCHOT assertions, while capturing longer PROCHOT events that could signify a more serious thermal problem within the system. Register 0x1E is the
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ADT7466
CONFIGURING THE ADT7466 THERM PIN AS AN OUTPUT
If PROCHOT monitoring is not required, Pin 7 can be configured as a THERM output by setting Bits 1:0 of Configuration Register 3 to 01. The user can preprogram system critical thermal limits. If the temperature exceeds a thermal limit by 0.25C, THERM asserts low. If the temperature is still above the thermal limit on the next monitoring cycle, THERM stays low. THERM remains asserted low until the temperature is equal to or below the thermal limit. Since the temperature for that channel is measured only every monitoring cycle, once THERM asserts, it is guaranteed to remain low for at least one monitoring cycle. The THERM pin can be configured to assert low if the TH1, TH2, external or internal temperature THERM limits are exceeded by 0.25C. The THERM limit registers are at locations 0x1F, 0x20, 0x21, and 0x22, respectively. Figure 32 shows how the THERM pin asserts low as an output in the event of a critical overtemperature.
THERM LIMIT 25C THERM LIMIT
TEMP
THERM
ADT7466 MONITORING CYCLE
Figure 31. Asserting THERM as an Output Based on Tripping THERM Limits
PROCHOT LIMIT (REG. 0x1E)
3.2s 1.6s 800ms 400ms 200ms 100ms 50ms 25ms 01234567 76543210
3.2s 1.6s 800ms 400ms 200ms 100ms 50ms 25ms
PROCHOT TIMER (REG. 0x0F)
PROCHOT
PROCHOT TIMER CLEARED ON READ COMPARATOR
IN
OUT
PCHT BIT (BIT 1) STATUS REGISTER 2 SMBALERT
LATCH RESET
Figure 32. Functional Diagram of the ADT7466 PROCHOT Monitoring Circuitry
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04711-031
CLEARED ON 1 = MASK READ PHOT BIT 1 MASK REGISTER 2 (REG. 0x13)
04711-030
ADT7466
FAN DRIVE
The ADT7466 contains two DACs to control fan speed. The full-scale output of these DACs is typically 2.2 V @ 2 mA, so they must be buffered in order to drive 5 V or 12 V fans. The output voltage of these DACs is controlled by data written to the DRIVE1 (0x40) and DRIVE2 (0x41) registers. Since fans do not turn on below a certain drive voltage, a significant proportion of the DAC range would be unusable; however, four other registers associated with fan speed control help the user to avoid this problem. Fan start-up voltage registers (0x30 and 0x31) determine the voltage initially applied to the fans at startup. This should be high enough to ensure that the fans start. Minimum speed registers (0x32 and 0x33) determine the minimum voltage that is applied to the fans. This should be high enough to keep the fans turning and less than the voltage required to start them. The speed registers associated with automatic fan speed control (AFC) are the maximum speed registers (0x34 and 0x35). They allow the maximum output from the DACs to be limited to less than the full-scale output. Some suitable fan drive circuits are shown in Figure 33 and Figure 34. Basically, voltage amplification is required to boost the full-scale output of the DAC to 5 V or 12 V, and the amplifier needs sufficient drive current to meet the drive requirements of the fan. Note that as the external transistor increases the open-loop gain of the op amp, it may be necessary to add a capacitor around the feedback loop to maintain stability.
12V 1/4 LM324 AOUT
PWM OR SWITCH MODE FAN DRIVE
Linear dc speed controllers, such as the ones described previously, waste power, which is dissipated as heat in the power transistor. To save power and reduce heat dissipation, it may be desirable to control the fan speed with a more efficient dc-dc converter or a pulse width modulated (PWM) speed controller. In this case, the DRIVE outputs of the ADT7466 provide the reference voltage for this circuit. To maximize efficiency, the controller can be switched off completely whenever the Fan 1 drive value falls below the value in the V_FAN_MIN register. When this happens, the FAN1_ON output goes low.
ADT7466
DRIVE1 V+ DRIVE VOLTAGE DC-DC OR PWM FAN SPEED CONTROLLER
FAN1 ON
SHUTDOWN
Figure 35. DC-DC or PWM Fan Speed Control
FAN SPEED MEASUREMENT
TACH Inputs Pin 2 and Pin 4 are tach inputs intended for fan speed measurement. The ADT7466 can measure the speed of 3-wire fans. Each 3-wire fan has two supply wires and a tach output wire. Signal conditioning in the ADT7466 accommodates the slow rise and fall times typical of fan tachometer outputs. The maximum input signal range is 0 V to 6.5 V, even when VCC is less than 5 V. If these inputs are supplied from fan outputs that exceed 0 V to 6.5 V, either resistive attenuation of the fan signal or diode clamping must be included to keep inputs within an acceptable range. Monitoring 3-Wire Fans Figure 36 to Figure 39 show circuits for most common 3-wire fan tach outputs. If the fan tach output has a resistive pull-up to VCC, it can be connected directly to the fan input, as shown in Figure 36.
FAN DRIVE VCC
R3 1k
Q1 2N2219A
Figure 33. Fan Drive Circuit with Op Amp and Emitter-Follower
5V OR 12V 1/4 LM324 DAC
PULLUP 4.7k TYP.
04711-032
R1 10k
R2 12k (5V) 43k (12V)
ADT7466
TACH TACH OUTPUT FAN SPEED COUNTER
R3 100k
Figure 34. Fan Drive Circuit with P-Channel MOSFET
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04711-033
R1 10k
R2 12k (5V) 43k (12V)
Figure 36. Fan with Tach Pull-Up to +VCC
04711-035
Q1 IRF9620
04711-034
ADT7466
If the fan output has a resistive pull-up to 12 V (or other voltage greater than 6.5 V), the fan output can be clamped with a Zener diode, as shown in Figure 37. The Zener diode voltage should be greater than VIH of the tach input but less than 6.5 V, allowing for the voltage tolerance of the Zener. A value of between 3 V and 5 V is suitable.
FAN DRIVE VCC
PULL-UP 4.7k TYP.
ADT7466
TACH OUTPUT TACH ZD1* ZENER FAN SPEED COUNTER
04711-036
Fan Speed Registers The fan counter does not count the fan tach output pulses directly because the fan speed can be less than 1000 rpm; it would take several seconds to accumulate a reasonably large and accurate count. Instead, the period of the fan revolution is measured by gating an on-chip 82 kHz oscillator into the input of a 16-bit counter for N periods of the fan tach output, as shown in Figure 40. The accumulated count is actually proportional to the fan tachometer period and inversely proportional to the fan speed.
CLOCK
*CHOOSE ZD1 VOLTAGE APPROX. 0.8 x VCC
TACH 1 2
04711-039
Figure 37. Fan with Tach. Pull-Up to Voltage >6.5 V, for Example, 12 V Clamped with Zener Diode.
If the fan has a strong pull-up (less than 1 k) to 12 V, or a totem pole output, a series resistor can be added to limit the Zener current, as shown in Figure 38. Alternatively, a resistive attenuator can be used, as shown in Figure 39. R1 and R2 should be chosen such that 2 V < VPULLUP x R2/(RPULLUP + R1 + R2) < 5 V The fan inputs have an input resistance of nominally 160 k to ground, which should be taken into account when calculating resistor values. With a pull-up voltage of 12 V and pull-up resistor less than 1 k, suitable values for R1 and R2 are 100 k and 47 k. This gives a high input voltage of 3.83 V.
FAN DRIVE VCC
Figure 40. Fan Speed Measurement
N, the number of pulses counted, is determined by the settings of Register 0x39 (fan pulses per revolution register). This register contains 2 bits for each fan, allowing 1, 2 (default), 3 or 4 tach pulses to be counted. The fan tachometer readings are 16-bit values consisting of a 2-byte read from the ADT7466. Table 24. Fan Speed Measurement Registers Register Description Default 0x48 TACH1 low byte 0xFF 0x49 TACH1 high byte 0xFF 0x4A TACH2 low byte 0xFF 0x4B TACH2 high byte 0xFF
Reading Fan Speed from the ADT7466
ADT7466
TACH OUTPUT PULL-UP TYP. < 1k OR TOTEM POLE R1 10k TACH ZD1* ZENER FAN SPEED COUNTER
04711-037
Measuring fan speeds involves a 2-register read for each measurement. The low byte should be read first, which causes the high byte to be frozen until both high and low byte registers are read. This prevents erroneous tach readings. The fan tachometer reading registers report the number of 12.2 s period clocks (82 kHz oscillator) gated to the fan speed counter from the rising edge of the first fan tach pulse to the rising edge of the third fan tach pulse, assuming two pulses per revolution is being counted. Since the device is essentially measuring the fan tach period, the higher the count value, the slower the fan is actually running. A 16-bit fan tachometer reading of 0xFFFF indicates either that the fan has stalled or that it is running very slowly (<75 rpm). A greater than comparison is performed when comparing with the high limit.
*CHOOSE ZD1 VOLTAGE APPROX. 0.8 x VCC
Figure 38. Fan with Strong Tach. Pull-Up to >VCC or Totem Pole Output, Clamped with Zener and Resistor.
FAN DRIVE VCC
ADT7466
<1k TACH OUTPUT R1* TACH R2*
04711-038
FAN SPEED COUNTER
*SEE TEXT
Figure 39. Fan with Strong Tach. Pull-Up to >VCC or Totem Pole Output, Attenuated with R1/R2.
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ADT7466
The actual fan tach period is being measured in this case. Therefore, when the fan tach limit is exceeded, a 1 is set for the appropriate status bit and can be used to generate an ALERT. The fan tach limit registers are 16-bit values consisting of 2 bytes.
Table 26. Fan Pulses Per Revolution Register
Fan 1:0 FAN1 3:2 FAN2 Default 2 pulses per revolution 2 pulses per revolution
Table 25. Fan Tach Limit Registers
Register 0x4C 0x4D 0x4E 0x4F Description TACH1 minimum low byte TACH1 minimum high byte TACH2 minimum low byte TACH2 minimum high byte Default 0xFF 0xFF 0xFF 0xFF
Table 27. Fan Pulses Per Revolution Values
Code 00 01 10 11 Pulses per Revolution 1 2 3 4
Fan Speed Measurement Rate
The fan tach readings are normally updated once every second. The FAST bit (Bit 3) of Configuration Register 3 (0x02) updates the fan tach readings every 250 ms, when set to 1. If any of the fans are not being driven by a fan drive output, but are powered directly from 5 V or 12 V, its associated dc bit in Configuration Register 3 should be set. This allows tach readings to be taken on a continuous basis for fans connected directly to a dc source.
The ADT7466 has a unique fan spin-up function. It spins the fan with the fan start-up voltage until two tach pulses are detected on the tach input. Once two pulses are detected, the fan drive goes to the expected running value. The advantage of this is that fans have different spin-up characteristics and take different times to overcome inertia. The ADT7466 runs the fans just fast enough to overcome inertia and is quieter on spin-up than fans programmed to spin-up for a given spin-up time.
Calculating Fan Speed
Assuming a fan with two pulses/revolution (and two pulses/revolution being measured) fan speed is calculated by
FAN START-UP TIMEOUT
To prevent false interrupts being generated as a fan spins up (since it is below running speed), the ADT7466 includes a fan start-up timeout function. This is the time limit allowed for two tach pulses to be detected on spin-up. For example, if a 2-second fan start-up timeout is chosen, and no tach pulses occur within two seconds of the start of spin-up, a fan fault is detected and flagged in Interrupt Status Register 1.
Fan Speed (rpm) = (82000 x 60)/Fan Tach Reading
where Fan Tach Reading is the 16-bit fan tachometer reading. For example, if TACH1 High Byte (Reg. 0x49) = 0x17 TACH1 Low Byte (Reg. 0x48) = 0xFF then fan speed in rpm is Fan 1 TACH reading = 0x17FF = 6143 decimal rpm = (82000 x 60)/Fan 1 TACH reading rpm = (82000 x 60)/6143 = 800 = fan speed
Start-Up Timeout Configuration (Reg. 0x38)
Bits 2:0 control the start-up timeout for DRIVE1. Bits 5:3 control the start-up timeout for DRIVE2.
Table 28. Start-Up Timeout Configuration
Code 000 001 010 011 100 101 110 111 Timeout No start-up timeout 100 ms 250 ms 400 ms 667 ms 1 second 2 seconds 4 seconds
Fan Pulses Per Revolution
Different fan models can output either 1, 2, 3, or 4 tach pulses per revolution. Once the number of fan tach pulses is determined, it can be programmed into the fan pulses per revolution register (0x39) for each fan. Alternatively, this register can be used to determine the number of pulses/revolution output by a given fan. By plotting fan speed measurements at 100% speed with different pulses/revolution settings, the smoothest graph with the lowest ripple determines the correct pulses/revolution value.
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ADT7466
AUTOMATIC FAN SPEED CONTROL
The ADT7466 has a local temperature sensor and a remote temperature channel, which can be connected to an on-chip diode-connected transistor on a CPU. In addition, the two analog input channels can be reconfigured for temperature measurement. Any or all of these temperature channels can be used as the basis for automatic fan speed control to drive fans according to system temperature. By running the fans at only the speed needed to maintain a desired temperature, acoustic noise is reduced. Reducing fan speed can also decrease system current consumption. To use automatic fan control (AFC), a number of parameters must be set up.
Fan Start Voltage (V_FAN_ON)
This is the minimum drive voltage from the DAC at which a fan starts running. This depends on the parameters of the fan and the characteristics of the fan drive circuit.
Minimum Fan Speed (V_FAN_MIN)
This is the minimum drive voltage from the DAC at which a fan keeps running, which is lower than the voltage required to start it. This depends on the parameters of the fan and the characteristics of the fan drive circuit.
Maximum Fan Speed
For acoustic reasons it may be desirable to limit the maximum rpm of the fans. These values are programmed into the maximum fan speed registers (0x34 and 0x35). During AFC, the fan speed is monitored and is never allowed to exceed the programmed limit, even if the AFC loop demands it. However, the maximum fan speed limit can be overridden by a THERM event, which sets the fan drive to full scale (full speed) for emergency cooling.
Which Temperature Channel Controls Which Fan?
This is determined by the AFC configuration registers (0x05 and 0x06). AFC1 configuration register controls Fan 1, and AFC2 configuration register controls Fan 2. Setting bits in these registers decides which temperature channels controls the fan.
Table 29. AFC Configuration Registers
Bit Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Description Fan controlled by TH1 or REM2 Fan controlled by TH2 Fan controlled by Remote Temperature 1 Fan controlled by local temperature Fan under manual control Fan at minimum speed Fan at start-up speed Fan at maximum speed
Operating Temperature Range
The temperature range over which AFC operates can be programmed by using the TMIN and TRANGE registers. TMIN is the temperature at which a fan starts and runs at minimum speed when in AFC mode. TRANGE is the temperature range over which AFC operates. Thus, if TMIN is set to 40C and TRANGE is set to 20C, the fan starts when the temperature exceeds 40C and the fan reaches maximum speed at a temperature of 60C.
Enhanced Acoustics
If more than one of the temperature channel Bits 0:3 are set, the channel that demands the highest fan speed takes control. When TH1 and TH2 are set up as AIN1 and AIN2, these pins still control the AFC loop if Bits 0:1 in the AFC configuration register are set. Bits 0:1 should not be set in analog input mode. If the manual control bit is set, AFC is switched off and the DRIVE registers can be programmed manually. This overrides any setting of the temperature channel bits. The maximum RPM registers, 0x34 and 0x35, should be set to 0x00 when the fans are under manual control. If the minimum speed bit is set, AFC is switched off and the fan runs at minimum speed. This overrides any setting of Bits 4:0. If the start-up speed bit is set, AFC is switched off and the fan runs at start-up speed. This overrides any setting of Bits 5:0. If the maximum speed bit is set, AFC is switched off and the fan runs at maximum speed. This overrides any setting of Bits 6:0. When fan speed is controlled automatically, a temperature event can cause the fan drive output to change instantaneously to a new value. The sudden subsequent change in fan speed can cause an audible noise pulse. To avoid this problem, the ADT7466 can be programmed so that the drive value changes in a series of small steps, using the enhanced acoustics register (0x36). Bits 2:0 of this register allow eight step sizes from 1 to 48 bits to be selected for Fan 1. Bits 5:3 do the same for Fan 2. When automatic fan control requires a change in drive value, the value changes by the step size once every 250 ms until the final value is reached. For example, if the step size is 3 and the drive value changes from 137 to 224, the drive value takes 29 ms x 250 ms to reach its final value. Enhanced acoustics for the Fan 1 output (DRIVE1) can be enabled by setting Bit 6 of the enhanced acoustics register, and by setting Bit 7 for Fan 2 (DRIVE2).
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ADT7466
AFC Loop Operation
The automatic fan speed control loop operates as follows. Once the temperature exceeds T_MIN, the ADT7466 outputs the voltage V_FAN_ON on its DRIVE pin. For Fan 1, FAN1 ON is also asserted. When the fan starts rotating reliably, the drive voltage is reduced to V_FAN_MIN. Reliable startup is determined when two tachometer pulses are sensed on the tach input. As the measured temperature increases, the voltage output by the ADT7466 also increases linearly. The rate with which the voltage output (fan speed) increases is controlled by the T_RANGE parameter. Once the measured fan speed reaches a programmable maximum limit, the fan speed does not increase further. This is to maintain low acoustics. If, however, the THERM fail safe limit is breached, the fans immediately run to full speed (0xFF). They continue to run at full speed until the temperature falls by a programmable hysteresis value below the THERM limit. Then the fan speed reduces to its value before the THERM limit is exceeded. As the temperature decreases, the fan speed decreases along the same curve. Once the temperature falls below T_MIN, the fan runs at V_FAN_MIN. If the temperature continues to decrease, the fan can continue to run at V_FAN_MIN, or if the temperature drops below a hysteresis value, the fan can be switched off completely. This is controlled by Bits 4:5 of Configuration Register 4. Setting these bits ensures that the fans never go below minimum speed. FAN 1 ON is also deasserted when the fan drive is set to 0 V. The fan speed is updated every 250 ms to 500 ms in the automatic fan speed control loop.
FAN DRIVE V FULL SPEED 2.25V (0xFF) T_THERM_HYS
STARTING THE FAN
Under normal conditions, the V_FAN_ON register sets DRIVE at a voltage sufficient to start the fan rotating. Fan startup is confirmed after two tach pulses are generated. 1. 2. 3. Set the initial V_FAN_ON by BIOS. Wait for two tach pulses (up to 2 seconds maximum). If successful, set the drive to V_FAN_MIN and follow the automatic slope. If not successful, increase the V_FAN_ON voltage on DRIVE by a programmed value (set in step size register) and return to Step 1. This sequence can be repeated five times or until DRIVE is set at full scale. If the fan still fails to start, the FANLOCK pin is asserted. 4. 5. Set the drive at 0 V (to avoid high power dissipation). Wait 1 minute and repeat the entire sequence. (This sequence recovers the situation if the fan is temporarily stalled due a mechanical reason such as jammed with a stick.)
FAN DRIVE V FULL SPEED 2.25V (0xFF)
V_FAN_ON V_FAN_MIN FAN OFF 0V (0x00)
TMIN
04711-041
TACHO
MAX FAN SPEED FAN SPIN UP FOR 2 TACH PULSES V_FAN_ON
Figure 42. Normal Fan Starting Timing Diagram
FAN DRIVE V FULL SPEED 2.25V (0xFF)
V_FAN_MIN FAN OFF 0V (0x00)
V_FAN_ON_STEP V_FAN_ON V_FAN_MIN FAN OFF 0V (0x00) FAN1_ON
04711-042
TMIN TRANGE TMIN_HYS
TMAX
TEMPERATURE
04711-040
2SEC
1MIN
T_THERM
Figure 41. Operation of AFC Loop
FAN_LOCK
Figure 43. Abnormal Fan Starting (Fan Stalled)
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ADT7466 XOR TEST MODE
The ADT7466 includes an XOR tree test mode. This mode is useful for in-circuit test equipment at board-level testing. By applying stimulus to the pins included in the XOR tree, it is possible to detect opens or shorts on the system board. Figure 44 shows the signals that are exercised in the XOR tree test mode. The XOR tree test is invoked by setting Bit 0 (XEN) of the XOR tree test enable register (0x42). Pin 7 should be configured as a PROCHOT input by setting Bit 1 (P7C1) of Configuration Register 3 (0x02). The PROCHOT mask bit (Reg. 0x13, Bit 1) should also be set.
SCL TACH1 SDA
PROCHOT
ALERT DRIVE1 TACH2
04711-043
Figure 44. ADT7466 XOR Tree
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ADT7466 APPLICATION CIRCUIT
Figure 45 shows a typical application circuit diagram for the ADT7466. The analog inputs are configured for thermistor temperature monitoring. Inputs D+ and D- are used to measure the temperature of a discrete transistor. In an actual application, every input and output may not be used. In this case, unused analog and digital inputs should be tied to ground. Pull-up resistors are required on SCL, SDA, FAN1_ON, PROCHOT/THERM, and FANLOCK. There are two drive outputs which control the speed of two fans. There are also two tach inputs from the fans for monitoring the fan speed.
FAN DRIVE CIRCUITRY
VCC 10k VCC 2k 2k SCLOCK SDATA SMB_ALERT VCC 10k VCC 10k
1 DRIVE1 2 TACH1 3 DRIVE2 4 TACH2 5 GND
FAN DRIVE CIRCUITRY
ADT7466
SCL 16 SDA 15 ALERT 14 REFOUT 13 AIN2/TH2/D2+ 12 AIN1/TH1/D2- 11 D1+ 10 2N3904 NPN
VCC 10k FAN1_ON/PROCHOT/THERM FANLOCK SIGNALS FAN FAILURE 10k VCC
TH1
TH2
6 VCC
7 FAN1_ON/PROCHOT/THERM 8 FANLOCK
Figure 45. Typical Application Circuit
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04711-045
D1- 9
REXT1
REXT2
ADT7466 ADT7466 REGISTER MAP
Table 30. ADT7466 Registers
Addr. R/W Name
0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C R R R R R R R R R R EXT1 EXT2 AIN1 AIN2 VCC REM1 LOC PCHT INT1 INT2 R/W CONF1 R/W CONF2 R/W CONF3 R/W CONF4 R/W CONF5 R/W AFC1 R/W AFC2
Description
Configuration 1 Configuration 2 Configuration 3 Configuration 4 Reserved AFC1 Configuration AFC2 Configuration Reserved Extended Resolution 1 Extended Resolution 2 AIN1(TH1)/REM2 Reading AIN2(TH2) Reading Vcc Reading Local Temp Reading PROCHOT Reading Interrupt Status 1 Interrupt Status 2 Interrupt Mask 1 Interrupt Mask 2 AIN1(TH1)/REM2 Low Limit AIN1(TH1)/REM2 High Limit AIN2(TH2) Low Limit AIN2(TH2) High Limit Vcc Low Limit Vcc High Limit Remote1 Temp Low Limit Remote1 Temp High Limit Local Temp Low Limit Local Temp High Limit PROCHOT Limit AIN1(TH1)/REM2 Therm Limit AIN2(TH2) Therm Limit Remote 1 Therm Limit Local Therm Limit Reserved AIN1(TH1)/REM2 Offset AIN2(TH2) Offset Remote1 Temp Offset Local Temp Offset AIN1(TH1)/REM2 TMIN AIN2(TH2) TMIN Remote1 TMIN Local TMIN TH1(REM2)/TH2
Bit 7
OBIN REM2 THER 2
Bit 6
Vcc SHDN THER1
Bit 5
TODIS RATE DC2 MIN2
Bit 4
FSPDIS AVG DC1 MIN1 MAN MAN 4 AIN2-0
Bit 3
FSPD FAST SNGL LOC LOC 3 VCC1
Bit 2
RDY REFZ BOOST CH2 REM REM 2 VCC0
Bit 1
LOCK CURR P7C1 CH1 TH2 TH2 1 REM1 LOC1
Bit 0
STRT RTYPE P7C0 CH0 TH1 TH1 0 REM0 LOC0 2 2 2 2 2 ASRT/ TMR0 FAN2 OVT FAN2 OVT 0 0 0 0 0 0 0 0 0 0 LIMT 0 0 0 0 0 0 0 0 0 0 0 0 0 TH2R0
LockDefault able
0x01 0x00 0xC0 0x00 0x00 0x0C 0x0C 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0xFF 0x00 0xFF 0x00 0xFF 0x00 0x7F 0x00 0x7F 0x00 0x64 0x64 0x64 0x64 0x00 0x00 0x00 0x00 0x00 0x5A 0x5A 0x5A 0x5A 0xCC Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes
MAX MAX 7 AIN1-1
STRT STRT 6 AIN1-0
MIN MIN 5 AIN2-1
9 9 9 9 TMR OOL
8 8 8 8 8 TMR AIN1(TH1)/ REM2 AIN1(TH1)/ REM2
7 7 7 7 7 TMR AIN2(TH2) TH2
6 6 6 6 6 TMR Vcc TH1 Vcc TH1 4 4 4 4 4 4 4 4 4 4 LIMT 4 4 4 4 4 4 4 4 4 4 4 4 4 TH1R0
5 5 5 5 5 TMR REM1 D2 REM D2 3 3 3 3 3 3 3 3 3 3 LIMT 3 3 3 3 3 3 3 3 3 3 3 3 3 TH2R3
4 4 4 4 4 TMR LOC D1 LOC D1 2 2 2 2 2 2 2 2 2 2 LIMT 2 2 2 2 2 2 2 2 2 2 2 2 2 TH2R2
3 3 3 3 3 TMR FAN1 PHOT FAN1 PHOT 1 1 1 1 1 1 1 1 1 1 LIMT 1 1 1 1 1 1 1 1 1 1 1 1 1 TH2R1
Remote1 Temp Reading 9
R/W MASK1 R/W MASK2 R/W AIN1LOW R/W AIN1HIGH R/W AIN2LOW R/W AIN2HIGH R/W VCCLOW R/W VCCHIGH R/W REM1LOW R/W REM1HIGH R/W LOCLOW R/W LOCHIGH R/W PCHTLIM R/W AIN1THERM R/W AIN2THERM R/W REM1THERM R/W LOCTHERM R/W R/W AIN1OFS R/W AIN2OFS R/W REM1OFS R/W LOCOFS R/W AIN1TMIN R/W AIN2TMIN R/W REM1TMIN R/W LOCTMIN R/W THTRANGE
OOL
AIN2(TH2) TH2
7 7 7 7 7 7 7 7 7 7 LIMT 7 7 7 7 7 7 7 7 7 7 7 7 7 TH1R3
6 6 6 6 6 6 6 6 6 6 LIMT 6 6 6 6 6 6 6 6 6 6 6 6 6 TH1R2
5 5 5 5 5 5 5 5 5 5 LIMT 5 5 5 5 5 5 5 5 5 5 5 5 5 TH1R1
Rev. 3 | Page 34 of 48 | www.onsemi.com
ADT7466
Addr. R/W Name
0x2D 0x2E 0x2F 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F 0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4A 0x4B 0x4C 0x4D 0x4E 0x4F 0x50 0x51 0x52 0x53 R/W R1LTRANGE R/W THTHYS R/W R1LTHYS R/W FAN1START R/W FAN2START R/W FAN1MIN R/W FAN2MIN R/W FAN1MAX R/W FAN2MAX R/W ENHANCED R/W FAULTINC R/W TIMEOUT R/W PULSES R/W R/W R/W R/W ID R R COMPANY REV
Description
TRANGE REM1,LOC TRANGE TH1,TH2 THyst Rem1/ Local THyst Fan1 Start-up Voltage Fan2 Start-up Voltage Fan1 Min Voltage Fan2 Min Voltage Fan1 Max RPM (High Byte) Fan2 Max RPM (High Byte) Enhanced Acoustics Fault Increment Startup Timeout Configuration Fan Pulses per Revolution Reserved Not Used Not Used Device ID Register Company ID Number Revision Number Drive 1 Drive 2 XOR Tree Test Enable Reserved Reserved (Target Monitor1) Reserved (Target Monitor2) Not Used Not Used
Bit 7
RM1R3 TH1TH3 RM1H3 7 7 7 7 7 7 FAN2EN 7
Bit 6
RM1R2 TH1TH2 RM1H2 6 6 6 6 6 6 FAN1EN 6
Bit 5
RM1R1 TH1TH1 RM1H1 5 5 5 5 5 5 FAN2-2 FAN2-2 ST2-2
Bit 4
RM1R0 TH1TH0 RM1H0 4 4 4 4 4 4 FAN2-1 FAN2-1 ST2-1
Bit 3
LOR3 TH2TH3 LOH3 3 3 3 3 3 3 FAN2-0 FAN2-0 ST2-0 FAN2
Bit 2
LOR2 TH2TH2 LOH2 2 2 2 2 2 2 FAN1-2 FAN1-2 ST1-2 FAN2 2
Bit 1
LOR1 TH2TH1 LOH1 1 1 1 1 1 1 FAN1-1 FAN1-1 ST1-1 FAN1 1
Bit 0
LOR0 TH2TH0 LOH0 0 0 0 0 0 0 FAN1-0 FAN1-0 ST1-0 FAN1 0
LockDefault able
0xCC 0x44 0x44 0x80 0x80 0x60 0x60 0x20 0x20 0x3F 0x3F 0x00 0x05 0x00 Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes
7
6
5
4
3
7 7 VER 7 7 7 7 7
6 6 VER 6 6 6 6 6
5 5 VER 5 5 5 5 5
4 4 VER 4 4 4 4 4
3 3 VER 3 3 3 3 3
2 2 VER 2 2 2 2 2
1 1 VER 1 1 1 1 1
0 0 VER 0 0 XEN 0 0 0
0x66 0x41 0x02 0x00 0x00 0x00 0x00 0x00 0x00 Yes Yes
R/W DRIVE 1 R/W DRIVE 2 R/W XOR R/W R/W R/W R/W R/W R R R R TACH1L TACH1H TACH2L TACH2H
Tach1 Low Byte Tach1 High Byte Tach2 Low Byte Tach2 High Byte Tach1 Minimum Low Byte Tach1 Minimum High Byte Tach2 Minimum Low Byte Tach2 Minimum High Byte Test Register1 Test Register2 Test Register3 Test Register4
7 15 7 15 7 7 7 7 7 7 7 7
6 14 6 14 6 6 6 6 6 6 6 6
5 13 5 13 5 5 5 5 5 5 5 5
4 12 4 12 4 4 4 4 4 4 4 4
3 11 3 11 3 3 3 3 3 3 3 3
2 10 2 10 2 2 2 2 2 2 2 2
1 9 1 9 1 1 1 1 1 1 1 1
0 8 0 8 0 0 0 0 0 0 0 0
0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0x00 0x00 0x00 0x00 Yes Yes Yes Yes
R/W TACH1LOW R/W TACH1HIGH R/W TACH2LOW R/W TACH2HIGH R/W TEST1 R/W TEST2 R/W TEST3 R/W TEST4
Rev. 3 | Page 35 of 48 | www.onsemi.com
ADT7466
REGISTER DETAILS
Configuration 1 Table 31. Register 0x00--Configuration Register 1 (Power-On Default = 0x01)
Bit No. 0 Name STRT Read/Write Read/Write Description Logic 1 enables monitoring, and PWM control outputs based on the limit settings programmed. Logic 0 disables monitoring and PWM control based on the default power-up limit settings. The limit values programmed are preserved even if a Logic 0 is written to this bit and the default settings are enabled. This bit becomes read only and cannot be changed once Bit 1 (LOCK bit) is written. All limit registers should be programmed by BIOS before setting this bit to 1. Lockable. Logic 1 locks all limit values to their current settings. Once this bit is set, all lockable registers become read only and cannot be modified until the ADT7466 is powered down and powered up again. This prevents rogue programs such as viruses from modifying critical system limit settings. Lockable. This bit is set to 1 by the ADT7466 to indicate that the device is fully powered up and ready to begin systems monitoring. When this bit is 1, it runs all fans at full speed. Power-on default is 0. This bit is not locked at any time. Logic 1 disables fan spin-up for two tach pulses. Instead, the DAC outputs go high for the entire fan spin-up timeout selected. When this bit is 1, the SMBus timeout feature is disabled. This allows the ADT7466 to be used with SMBus controllers that cannot handle SMBus timeouts. Lockable. When this bit is 1, the ADT7466 rescales its VCC pin to measure a 5 V supply. When this bit is 0, the ADT7466 measures VCC as a 3.3 V supply. Lockable. When this bit is 0 (default) temperature data format is binary. When this bit is 1, format is offset binary.
1
LOCK
Write Once
2 3 4 5 6 7
RDY FSPD FSPDIS TODIS VCC OBIN
Read Only Read/Write Read/Write Read/Write Read/Write Read/Write
Configuration 2
This register becomes read only when the Configuration Register 1 lock bit is set to 1. Additional attempts to write to this register have no effect.
Table 32. Register 0x01--Configuration Register 2 (Power-On Default = 0x00)
Bit No. 0 1 2 3 4 5 6 7 Name RTYPE CURR REFZ Unused AVG RATE SHDN REM2 Read/Write Read/Write Read/Write Read/Write - Read/Write Read/Write Read/Write Read/Write Description When this bit is cleared (default), thermistor normalization is optimized for 100 k thermistors. When this bit is set, it is optimized for 10 k thermistors. This bit sets the thermal diode current. It should be left at 0. Setting this bit makes the REFOUT pin high impedance. Unused. Write ignored. Reads back 0. When AVG is 1, averaging on the temperature and voltage measurements is turned off. This allows measurements on each channel to be made much faster. If averaging is turned off and measurement set to single channel mode, the RATE bit sets the conversion rate. 0 = 32 conversions/second; 1 = 4 conversions/second. When SHDN is 1, the ADT7466 goes into shutdown mode. Both DAC outputs are set to 0 V to switch off both fans. The DAC registers read back 0x00 to indicate that the fans are not being driven. Setting this bit configures AIN1 and AIN2 for connection of a second thermal diode. Setting this bit overrides THER1 and THER2 in Configuration Register 3.
Rev. 3 | Page 36 of 48 | www.onsemi.com
ADT7466
Configuration 3
This register becomes read only when the Configuration Register 1 lock bit is set to 1. Additional attempts to write to this register have no effect. Bits 4:5 are not locked.
Table 33. Register 0x02--Configuration Register 3 (Power-On Default = 0xC0)
Bit No. 1:0 Name P7CONFIG Read/Write Read/Write Description These bits configure Pin 7 as either FAN1_ON output, THERM output or PROCHOT input. 00 = FAN1_ON output 01 = THERM output 1X = PROCHOT input 2 3 4 5 6 7 BOOST FAST DC1 DC2 THER2 THER1 Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write When BOOST is set to 1, assertion of PROCHOT causes all fans to run at 100% duty cycle for fail safe cooling. Setting this bit to 1 enables fast tach measurements on all channels. This increases the tach measurement rate from once a second, to one every 250 ms (4x). Setting this bit to 1 enables tach measurements to be continuously made on TACH1. Not lockable. Setting this bit to 2 enables tach measurements to be continuously made on TACH2. Not lockable. Setting this bit to 1 configures AIN1 as a thermistor input. Setting this bit to 0 configures for analog input. Setting this bit to 1 configures AIN2 as a thermistor input. Setting this bit to 0 configures for analog input.
Configuration Register 4 Table 34. Register 0x03--Configuration Register 4 (Power-On Default = 0x00)
Bit No. 2:0 Name CH2:0 R/W Read/Write Description These bits select the input channel when SNGL bit is set. 011 = Remote 1 temperature 100 = Local temperature 101 = Remote 2 temperature Setting this bit selects single channel measurement. When this bit is set, Fan 1 never goes below minimum speed setting. When this bit is set, Fan 2 never goes below minimum speed setting. Unused. Write ignored. Reads back 0. Unused. Write ignored. Reads back 0.
3 4 5 6 7
SNGL MIN1 MIN2 Unused Unused
Read/Write Read/Write Read/Write Read only Read only
AFC1 Configuration
If more than one of Bits 0:3 are set, the fan speed is controlled by whichever temperature channel demands the highest fan speed.
Table 35. Register 0x05--AFC Configuration Register 1 (Power-On Default = 0x0C)
Bit No. 0 1 2 3 4 5 6 7 Name TH1/REM2 TH2 REM1 LOC MAN MIN STRT MAX Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Description When this bit is set, Fan 1 speed is controlled by TH1 if Pin 11 is configured for thermistor, or by Thermal Diode 2 if Pin 11 is configured for thermal diode. When this bit is set, Fan 1 speed is controlled by TH2 if Pin 12 is configured for thermistor. When this bit is set, Fan 1 speed is controlled by Remote Temperature Input 1. When this bit is set, Fan 1 speed is controlled by local temperature input. When this bit is set, Fan 1 speed is under user control by writing directly to the DRIVE1 register. This overrides all lower bit settings When this bit is set, Fan 1 runs at minimum speed. This overrides all lower bit settings. When this bit is set, Fan 1 runs at start-up speed. This overrides all lower bit settings. When this bit is set, Fan 1 runs at maximum speed. This overrides all lower bit settings.
Rev. 3 | Page 37 of 48 | www.onsemi.com
ADT7466
AFC2 Configuration
If more than one of Bits 0:3 are set, the fan speed is controlled by whichever temperature channel demands the highest fan speed.
Table 36. Register 0x06--AFC Configuration Register 2 (Power-On Default = 0x0C)
Bit No. 0 1 2 3 4 5 6 6 Name TH1/REM2 T H2 REM1 LOC MAN MIN STRT MAX Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Description When this bit is set, Fan 2 speed is controlled by TH1 if Pin 11 is configured for thermistor, or by Thermal Diode 2 if Pin 11 is configured for thermal diode. When this bit is set, Fan 2 speed is controlled by TH2 if Pin 12 is configured for thermistor. When this bit is set, Fan 2 speed is controlled by Remote Temperature Input 1. When this bit is set, Fan 2 speed is controlled by the local temperature input. When this bit is set, Fan 2 speed is under user control by writing directly to the DRIVE2 register. This overrides all lower bit settings. When this bit is set, Fan 2 runs at minimum speed. This overrides all lower bit settings. When this bit is set, Fan 2 runs at startup speed. This overrides all lower bit settings. When this bit is set, Fan 2 runs at maximum speed. This overrides all lower bit settings.
Extended Resolution 1 Table 37. Register 0x08--Extended Resolution Register 1 (Power-On Default = 0x00)
Bit No. 0 1 2 3 4 5 6 7 Name REM0 REM1 VCC0 VCC1 AIN2-0 AIN2-1 AIN1-0 AIN1-1 Read/Write Read only Read only Read only Read only Read only Read only Read only Read only Description LSB of remote temperature reading. Bit 1 of remote temperature reading. LSB of VCC reading. Bit 1 of VCC reading. LSB of AIN2 reading. Bit 1 of AIN2 reading LSB of AIN1 reading. Bit 1 of AIN1 reading.
Extended Resolution 2 Table 38. Register 0x09--Extended Resolution Register 2 (Power-On Default = 0x00)
Bit No. 0 1 2 3 4 5 6 7 Name LOC0 LOC1 Unused Unused Unused Unused Unused Unused Read/Write Read only Read only Read only Read only Read only Read only Read only Read only Description LSB of local temperature reading. Bit 1 of local temperature reading. Not used. Reads back 0. Not used. Reads back 0. Not used. Reads back 0. Not used. Reads back 0. Not used. Reads back 0. Not used. Reads back 0.
Voltage Reading
If the extended resolution bits of these readings are also being read, Extended Resolution Register 1 (0x08) should be read first. Once the extended resolution register is read, it and the associated MSB reading registers are frozen until read.
Table 39. Voltage Reading Registers (Power-On Default = 0x00)
Register Address 0x0A 0x0B 0x0C Read/Write Read only Read only Read only Description AIN1(TH1)/REM2 reading (8 MSBs of reading). AIN2(TH2) reading (8 MSBs of reading). VCC reading. Measures VCC through the VCC pin (8 MSBs of reading).
Rev. 3 | Page 38 of 48 | www.onsemi.com
ADT7466
Temperature Reading
If the extended resolution bits of these readings are also being read, the extended resolution registers (0x08, 0x09) should be read first. Once the extended resolution register gets read, all associated MSB reading registers get frozen until read. Both the extended resolution register and the MSB registers are frozen.
Table 40. Temperature Reading Registers (Power-On Default = 0x00)
Register Address 0x0D 0x0E Read/Write Read only Read only Description Remote Temperature 1 reading (8 MSBs of reading). Local temperature reading (8 MSBs of reading).
PROCHOT Table 41. Register 0x0F--PROCHOT Register (Power-On Default = 0x00)
Bit No. 7:1 0 Name TMR ASRT/TMR0 Read/Write Read only Read only Description Times for how long THERM input is asserted. These 7 bits read 0 until the PROCHOT assertion time exceeds 45.52 ms. Set high on the assertion of the THERM input. Cleared on read. If the PROCHOT assertion time exceeds 45.52 ms, this bit is set and becomes the LSB of the 8-bit TMR reading. This allows PROCHOT assertion times from 45.52 ms to 5.82 seconds to be reported back with a resolution of 22.76 ms.
Interrupt Status 1 Table 42. Register 0x10--Interrupt Status Register 1 (Power-On Default = 0x00)
Bit No. 0 1 2 3 4 5 6 7 Name FAN2 FAN1 LOC REM1 VCC AIN2(TH2) AIN1(TH1)/REM2 OOL Read/Write Read only Read only Read only Read only Read only Read only Read only Read only Description Setting this bit to 1 indicates that Fan 2 has dropped below minimum speed or has stalled. This bit is not set when the DRIVE2 output is off. Setting this bit to 1 indicates that Fan 1 has dropped below minimum speed or has stalled. This bit is not set when the DRIVE1 output is off. Setting this bit to 1 indicates that the local temperature reading is out of limit. This bit is cleared on a read of the status register only if the error condition clears. Setting this bit to 1 indicates that Remote Temperature 1 reading is out of limit. This bit is cleared on a read of the status register only if the error condition clears. Setting this bit to 1 indicates that the VCC reading is out of limit. This bit is cleared on a read of the status register only if the error condition clears. Setting this bit to 1 indicates that the AIN2(TH2) reading is out of limit. This bit is cleared on a read of the status register only if the error condition clears. Setting this bit to 1 indicates that the AIN1(TH1)/REM2 reading is out of limit. This bit is cleared on a read of the status register only if the error condition clears. Setting this bit to 1 indicates that an out-limit event is latched in Status Register 2. This bit is a logical OR of all status bits in Status Register 2. Software can test this bit in isolation to determine whether any of the voltage, temperature, or fan speed readings represented by Status Register 2 are out of limit. This saves the need to read Status Register 2 during every interrupt or polling cycle.
Rev. 3 | Page 39 of 48 | www.onsemi.com
ADT7466
Interrupt Status 2 Table 43. Register 0x11--Interrupt Status Register 2 (Power-On Default = 0x00)
Bit No. 0 1 2 3 4 5 6 7 Name OVT PHOT D1 D2 TH1 TH2 Unused Unused Read/Write Read only Read only Read only Read only Read only Read only Read only Read only Description Setting this bit to 1 indicates that one of the THERM overtemperature limits has been exceeded. This bit is cleared automatically when the temperature drops below THERM - THYST. If Pin 7 is configured as the input for PROCHOT monitoring, this bit is set when the PROCHOT assertion time exceeds the limit programmed in the PROCHOT limit register (0x1E). Setting this bit to 1 indicates either an open or a short circuit on the Thermal Diode 1 inputs. Setting this bit to 1 indicates either an open or a short circuit on the Thermal Diode 2 inputs. Setting this bit to 1 indicates either an open or a short circuit on the TH1 input. Setting this bit to 1 indicates either an open or a short circuit on the TH2 input. Not used. Reads back 0. Not used. Reads back 0.
Interrupt Mask 1 Table 44. Register 0x12--Interrupt Mask Register 1 (Power-On Default = 0x00)
Bit No. 0 1 2 3 4 5 6 7 Name FAN2 FAN1 LOC REM VCC AIN2(TH2) AIN1 /TH1/REM2 OOL Read/Write Read only Read only Read only Read only Read only Read only Read only Read only Description Setting this bit masks the Fan 2 interrupt from the ALERToutput. Setting this bit masks the Fan 1 interrupt from the ALERT output. Setting this bit masks the local temperature. interrupt from the ALERT output. Setting this bit masks the remote temperature interrupt from the ALERT output. Setting this bit masks the VCC interrupt from the ALERT output. Setting this bit masks the AIN2(TH2) interrupt from the ALERT output. Setting this bit masks the AIN1(TH1)/REM2 interrupt from the ALERT output. Setting this bit masks the OOL interrupt from the ALERT output.
Interrupt Mask 2 Table 45. Register 0x13--Interrupt Mask Register 2 (Power-On Default = 0x00)
Bit No. 0 1 2 3 4 5 6 7 Name OVT PHOT D1 D2 TH1 TH2 Unused Unused Read/Write Read only Read only Read only Read only Read only Read only Read only Read only Description Setting this bit masks the OVT interrupt from ALERT output. Setting this bit masks the THERM interrupt from ALERT output. Setting this bit masks the Thermal Diode 1 fault interrupt from ALERT output. Setting this bit masks Thermal Diode 2 fault interrupt from ALERT output. Setting this bit masks the TH1 fault interrupt from ALERT output. Setting this bit masks the TH2 fault interrupt from ALERT output. Not used. Reads back 0. Not used. Reads back 0.
Rev. 3 | Page 40 of 48 | www.onsemi.com
ADT7466
Voltage Limit
Setting the Configuration Register 1 lock bit has no effect on these registers. High limits: An interrupt is generated when a value exceeds its high limit (> comparison). Low limits: An interrupt is generated when a value is equal to or below its low limit ( comparison).
Table 46. Voltage Limit Registers
Register Address 0x14 0x15 0x16 0x17 0x18 0x19 Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Description AIN1(TH1)/REM2 low limit. AIN1(TH1)/REM2 high limit. AIN2(TH2) low limit. AIN2(TH2) high limit. VCC low limit. VCC high limit. Power-On Default 0x00 0xFF 0x00 0xFF 0x00 0xFF
Temperature Limit
Setting the Configuration Register 1 lock bit has no effect on these registers. When the temperature readings are in offset binary format, an offset of 64 degrees (0x40 or 0100000) must be added to all temperature and THERM limits. For example, if the limit is 50C the actual programmed limit is 114. High limits: An interrupt is generated when a value exceeds its high limit (> comparison). Low limits: An interrupt is generated when a value is equal to or below its low limit ( comparison).
Table 47. Temperature Limit Registers
Register Address 0x1A 0x1B 0x1C 0x1D Read/Write Read/Write Read/Write Read/Write Read/Write Description Remote 1 Temperature low limit. Remote 1 Temperature high limit. Local temperature low limit. Local temperature high limit. Power-On Default 0x00 0x7F 0x00 0x7F
PROCHOT Limit
This is an 8-bit limit with a resolution of 22.76 ms allowing PROCHOT assertion limits of 45.52 ms to 5.82 seconds to be programmed. If the PROCHOT assertion time exceeds this limit, Bit 1 of Interrupt Status Register 2 (0x11) is set. If the limit value is 0x00, an interrupt is generated immediately upon assertion of the THERM input.
Table 48. Register 0x1E--PROCHOT Limit Register (Power-On Default = 0x00)
Bit No. 7:0 Name LIMT Read/Write Read/Write Description Sets maximum PROCHOT assertion length allowed before an interrupt is generated.
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ADT7466
THERM Limit
If any temperature measured exceeds its THERM limit, both DRIVE outputs drive their fans at maximum output. This is a failsafe mechanism incorporated to cool the system in the event of a critical overtemperature. It also ensures some level of cooling in the event that software or hardware locks up. If set to 0x00, this feature is disabled. The DRIVE output remains at 0xFF until the temperature drops below THERM limit - hysteresis. If the THERM pin is programmed as an output, exceeding these limits by 0.25C can cause the THERM pin to assert low as an output. These registers become read only when the Configuration Register 1 lock bit is set to 1. Additional attempts to write to these registers have no effect.
Table 49. THERM Limit Registers
Register Address 0x1F 0x20 0x21 0x22 Read/Write Read/Write Read/Write Read/Write Read/Write Description AIN1/TH1REM2 THERM limit. AIN2(TH2) THERM limit. Remote 1 THERM limit. Local THERM limit. Power-On Default 0x64 (100C) 0x64 (100C) 0x64 (100C) 0x64 (100C)
Temperature Offset
These registers contain an 8-bit, twos complement offset value that is automatically added to or subtracted from the temperature reading to compensate for any systematic errors such as those caused by noise pickup. LSB value = 1C. This register becomes read only when the Configuration Register 1 lock bit is set to 1. Additional attempts to write to this register have no effect.
Table 50. Temperature Offset Registers
Register Address 0x24 0x25 0x26 0x27 Read/Write Read/Write Read/Write Read/Write Read/Write Description AIN1(TH1)/REM2 offset. AIN2(TH2) offset. Remote 1 offset. Local offset. Power-On Default 0x00 0x00 0x00 0x00
TMIN
These registers contain the TMIN temperatures for automatic fan control (AFC). These are the temperatures above which the fan starts to operate. The data format is either binary or offset binary, the same as the temperature reading, depending on which option is chosen by setting or clearing Bit 7 of Configuration Register 1. These registers become read only when the Configuration Register 1 lock bit is set to 1. Additional attempts to write to these registers have no effect.
Table 51. TMIN Registers
Register Address 0x28 0x29 0x2A 0x2B Read/Write Read/Write Read/Write Read/Write Read/Write Description AIN1(TH1)/REM2 TMIN. AIN2(TH2) TMIN. Remote 1 TMIN. Local TMIN. Power-On Default 0x5A (90C) 0x5A (90C) 0x5A (90C) 0x5A (90C)
Rev. 3 | Page 42 of 48 | www.onsemi.com
ADT7466
Table 52. TMIN Codes
Temperature -64C 0C 1C 10C 25C 50C 75C 100C 125C 127C 191C Binary 0 000 0000 0 000 0000 0 000 0001 0 000 1010 0 001 1001 0 011 0010 0 100 1011 0 110 0100 0 111 1101 0 111 1111 0 111 1111 Offset Binary 0 000 0000 0 100 0000 0 100 0001 0 100 1010 0 101 1001 0 111 0010 1 000 1011 1 010 0100 1 011 1101 1 011 1111 1 111 1111
THT Range Table 53. Register 0x2C--THTRANGE Register (Power-On Default = 0xCC)
Bit No. 3:0 Name TH2R Read/Write Read/Write Description These bits set the temperature range over which AFC operates for the TH2 input. The fan starts operating at TM and reaches full speed at TM+ TR (where TM is the temperature set by the TMIN code, and TR is the temperature range set by the TRANGE code). These bits set the temperature range over which AFC operates for the TH1 or REM2 input. The fan starts operating at TM and reaches full speed at TM+ TR (where TM is the temperature set by the TMIN code, and TR is the temperature range set by the TRANGE code).
7:4
TH1R
Read/Write
Remote and Local TRANGE Table 54. Register 0x2D--Remote and Local TRANGE Register (Power-On Default = 0xCC)
Bit No. 3:0 Name LOR Read/Write Read/Write Description These bits set the temperature range over which AFC operates for the local temperature input. The fan starts operating at TM and reaches full speed at TM + TR (where TM is the temperature set by the TMIN code, and TR is the temperature ranges set by the TRANGE code). These bits set the temperature range over which AFC operates for the Remote 1 (D1) temperature input. The fan starts operating at TM and reaches full speed at TM + TR (where TM is the temperature set by the TMIN code, and TR is the temperature range set by the TRANGE code). TRANGE 2C 2.5C 3.33C 4C 5C 6.67C 8C 10C 13.33C 16C 20C 26.67C 32C (default) 40C 53.33C 80C
7:4
RMR
Read/Write
Table 55. TRANGE Codes
Bits 7:4 or 3:0 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111
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ADT7466
TH1/TH2 Hysteresis Table 56. Register 0x2E--TH1/TH2 Hysteresis Register (Power-On Default = 0x44)
Bit No. 7:4 3:0 Name TH1TH TH2TH Read/Write Read/Write Read/Write Description This nibble contains the temperature hysteresis value for TH1/REM2. 0x0 = 0C to 0xF = 15C. This nibble contains the temperature hysteresis value for TH2. 0x0 = 0C to 0xF = 15C.
REM/LOC Hysteresis Table 57. Register 0x2F--REM/LOC Hysteresis Register (Power-On Default = 0x44)
Bit No. 7:4 3:0 Name RM1H LOH Read/Write Read/Write Read/Write Description This nibble contains the temperature hysteresis value for remote temperature input. 0x0 = 0C to 0xF = 15C. This nibble contains the temperature hysteresis value for local temperature input. 0x0 = 0C to 0xF = 15C.
Fan Start-Up Voltage
This is the voltage output from the fan drive output for two tach periods after it first starts up. Taking gain into account, the fan drive amplifier should be chosen so the voltage applied to the fan is sufficiently high to ensure that the fan starts.
Table 58. Fan Start-Up Voltage Registers (Power-On Default = 0x80)
Register Address 0x30 0x31 Read/Write Read/Write Read/Write Description Fan 1 start-up voltage. Fan 2 start-up voltage.
Fan Maximum Voltage
This is the minimum voltage output from the fan drive output after the fan spins up, in the absence of any other speed control input.
Table 59. Fan Minimum Voltage Registers (Power-On Default = 0x60)
Register Address 0x32 0x33 Read/Write Read/Write Read/Write Description Fan 1 minimum voltage. Fan 2 minimum voltage.
Fan Maximum RPM
This is the maximum RPM that the fan can run at in AFC mode.
Table 60. Fan Maximum RPM Registers (Power-On Default = 0x20)
Register Address 0x34 0x35 Read/Write Read/Write Read/Write Description Fan 1 maximum RPM. Fan 2 maximum RPM.
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ADT7466
Enhanced Acoustics Table 61. Register 0x36--Enhanced Acoustics Register (Power-On Default = 0x3F)
Bit No. 2:0 5:3 Name FAN1 Step FAN2 Step Read/Write Read/Write Read/Write Description These bits set the step size by which the DRIVE1 and DRIVE2 PWM output duty-cycle can change when enhance acoustics mode is selected. 000 = 1 bit 001 = 2 bits 010 = 3 bits 011 = 5 bits 100 = 8 bits 101 = 12 bits 110 = 24 bits 111 = 48 bits When this bit is set to 1, enhanced acoustics are enabled for Fan 1.
6
7
Enable Fan1 Enhanced Acoustics Enable Fan2 Enhanced Acoustics
Read/Write
Read/Write
When this bit is set to 1, enhanced acoustics are enabled for Fan 2.
Fault Increment Table 62. Register 0x37--Fault Increment Register (Power-On Default = 0x3F)
Bit No. 2:0 5:3 Name FAN1Fault FAN2 Fault Read/Write Read/Write Read/Write Description These bits set the step size by which the DRIVE1 and DRIVE2 PWM output duty-cycle can change in fan fault mode. 000 = 1 bit 001 = 2 bits 010 = 3 bits 011 = 5 bits 100 = 8 bits 101 = 12 bits 110 = 24 bits 111 = 48 bits Unused. Write ignored. Reads back 0.
7:6
Unused
-
Start-Up Timeout Configuration Table 63. Register 0x38--Start-Up Timeout Configuration Register (Power-On Default = 0x00)
Bit No. 2:0 5:3 Name ST1 ST2 Read/Write Read/Write Read/Write Description These bits set the start-up timeout for Fan 1. These bits set the start-up timeout for Fan 2. 000 = No start-up timeout 001 = 100 ms 010 = 250 ms 011 = 400 ms 100 = 667 ms 101 = 1second 110 = 2 seconds 111 = 4 seconds Unused. Write ignored. Reads back 0.
7:6
Unused
-
Rev. 3 | Page 45 of 48 | www.onsemi.com
ADT7466
Fan Pulses Per Revolution Table 64. Register 0x39--Fan Pulses Per Revolution Register (Power-On Default = 0x05)
Bit No. 1:0 Name FAN1 Read/Write Read/Write Description Sets number of pulses to be counted when measuring FAN1 speed. Can be used to determine fan's pulses per revolution number for unknown fan type. Pulses Counted 00 = 1 01 = 2 (default) 10 = 3 11 = 4 Sets number of pulses to be counted when measuring FAN2 speed. Can be used to determine fan's pulses per revolution number for unknown fan type. Pulses Counted 00 = 1 01 = 2 (default) 10 = 3 11 = 4 Unused. Write ignored. Reads back 0.
3:2
FAN2
Read/Write
7:4
Unused
-
Information Registers Table 65. Register 0x3D--Device ID Register (Power-On Default = 0x66)
Bit No. 7:0 Name Reserved Read/Write Read only Description Contains device ID number.
Table 66. Register 0x3E--Company Id Register (Power-On Default = 0x41)
Bit No. 7:0 Name Reserved Read/Write Read only Description Contains company ID number.
Table 67. Register 0x3F--Revision Number Register (Power-On Default = 0x02)
Bit No. 7:0 Name Reserved Read/Write Read only Description Contains device revision level.
Fan Drive (DAC)
These registers reflect the drive value of each fan at any given time. When in automatic fan speed control mode, the ADT7466 reports the drive values back through these registers. The fan drive values vary according to temperature in automatic fan speed control mode. During fan startup, these registers report 0x00. In software mode, the fan drive outputs can be set to any value by writing to these registers.
Table 68. Fan Drive (DAC) Registers (Power-On Default = 0x00)
Register Address 0x40 0x41 Read/Write Read/Write Read/Write Description DRIVE1, Current Fan 1 drive value. DRIVE2, Current Fan 2 drive value.
XOR Tree Test Enable
This register becomes read only when the Configuration Register 1 lock bit is set to 1. Additional attempts to write to this register have no effect.
Table 69. Register 0x42--XOR Tree Test Enable (Power-On Default = 0x00)
Bit No. 7:1 0 Name Reserved XEN Read/Write - Read/Write Description Unused. Do not write to these bits. If the XEN bit is set to 1, the device enters the XOR tree test mode. Clearing the bit removes the device from the XOR test mode.
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ADT7466
Fan Tachometer Reading
These registers count the number of 12.43 s periods (based on a local 82 kHz clock) that occur between a number of consecutive fan tach pulses (default = 2). The number of tach pulses used to count can be changed by using the fan pulses per revolution register (0x39). This allows the fan speed to be accurately measured. Since a valid fan tachometer reading requires two bytes to be read, the low byte must be read first. Both the low and high bytes are then frozen until read. At power-on, these registers contain 0x0000 until such time as the first valid fan tach measurement is read into these registers. This prevents false interrupts from occurring while the fans are spinning up. A count of 0xFFFF indicates that a fan is
* * * *
Stalled or blocked (object jamming the fan). Failed (internal circuitry destroyed). Not populated (the ADT7466 expects to see a fan connected to each tach. If a fan is not connected to that tach, its tach minimum high and low byte should be set to 0xFFFF). 2-wire instead of 3-wire.
Read/Write Read only Read only Read only Read only Description TACH1 low byte TACH1 high byte TACH2 low byte TACH2 high byte
Table 70. Fan Tachometer Reading Registers (Power-On Default = 0xFF)
Register Address 0x48 0x49 0x4A 0x4B
Fan Tachometer Limit
Exceeding any of the tach limit registers by 1 indicates that the fan is running too slowly or has stalled. The appropriate status bit is set in Interrupt Status Register 1 to indicate the fan failure. Setting the Configuration Register 1 lock bit has no effect on these registers.
Table 71. Fan Tachometer Limit Registers (Power-On Default = 0xFF)
Register Address 0x4C 0x4D 0x4E 0x4F Read/Write Read/Write Read/Write Read/Write Read/Write Description TACH 1 minimum low byte TACH 1 minimum high byte TACH 2 minimum low byte TACH 2 minimum high byte
Manufacturer's Test
These registers are for manufacturer's use only and should not be read or written to in normal use. These registers become read only when the Configuration Register 1 lock bit is set to 1. Additional attempts to write to these register have no effect.
Table 72. Register 0x3F--Manufacturers Test Registers (Power-On Default = 0x00)
Register Address 0x50 0x51 0x52 0x53 Read/Write Read/Write Read/Write Read/Write Read/Write Description Manufacturer's Test Register 1 Manufacturer's Test Register 2 Manufacturer's Test Register 3 Manufacturer's Test Register 4
Rev. 3 | Page 47 of 48 | www.onsemi.com
ADT7466 OUTLINE DIMENSIONS
0.193 BSC
16 9
0.154 BSC
1 8
0.236 BSC
PIN 1 0.065 0.049 0.069 0.053
0.010 0.025 0.004 BSC COPLANARITY 0.004
0.012 0.008
SEATING PLANE
0.010 0.006
8 0
0.050 0.016
COMPLIANT TO JEDEC STANDARDS MO-137AB
Figure 46. 16-Lead Shrink Small Outline Package [QSOP] (RQ-16) Dimensions shown in inches
ORDERING GUIDE
Model ADT7466ARQ Z1 ADT7466ARQ Z-REEL1 ADT7466ARQ Z-RL71 EVAL-ADT7466EB
1
Temperature Range -40C to +125C -40C to +125C -40C to +125C
Package Description 16-Lead QSOP 16-Lead QSOP 16-Lead QSOP Evaluation Board
Package Option RQ-16 RQ-16 RQ-16
Z = Pb-free part.
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303-675-2175 or 800-344-3860 Toll Free USA/Canada Fax: 303-675-2176 or 800-344-3867 Toll Free USA/Canada Email: orderlit@onsemi.com N. American Technical Support: 800-282-9855 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 421 33 790 2910 Japan Customer Focus Center Phone: 81-3-5773-3850 ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative
Rev. 3 | Page 48 of 48 | www.onsemi.com

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